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Observer asimons
Observer
4,852 Views
Registered: ‎11-19-2010

Is this proper verilog syntax?

I inherited a verilog design.  One module has parameterized values.  Its module definition looks like:

 

module myModule #(parameter param1 = 6'd38, param2 = 5'24) 
   (
      input in1,
      input in2
   );

...

endmodule

 

Is this a valid way to create a module with changeable parameters?  I haven't seen this exact form anywhere on the web, and its proper operation is suspect in my system.  Thanks!

 

Alan Simons

 

 

 

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1 Reply
Instructor
Instructor
4,831 Views
Registered: ‎08-14-2007

Re: Is this proper verilog syntax?

That syntax was introduced in Verilog 2001.  It is the equivalent of the old Verilog 95 syntax:

 

module myModule (  in1, in2 );

 

parameter param1 = 6'd38;

parameter param2 = 5'd24;

 

input in1;

input in2;

 

. . .

 

endmodule

 

Also introduced in Verilog 2001 is the new syntax for instantiating modules with parameters:

 

myModule

#(

  .param1  (6'd38),

  .param2  (5'd24)

)

  myInstance

(

  .in1  (x),

  .in2  (y)

);

 

The use of the new module declaration with parameters at the top allows the use of parameters in the port list when you declare the port types in the port list rather than below it.

 

For example you could have:

 

. . .

  input [param1-1:0] in1,

. . .

 

Without the new parameter syntax, the parameter would be declared after it was used in the port list, which is still not allowed in Verilog 2001.

-- Gabor