03-21-2017 08:00 AM
I'm having a hard time with the JESD204B core in understanding the way clocks are used. I have my own Verilog code running with what should be the same clock speed as the JESD204B reference clock. Can I use the JESD input clock? The problem is that the core takes a differential input and then uses "clocking support" with an MMCM and BUFG internally to provide the clock to the core. I therefore can't really use the clock externally without adding my own MMCM and BUFG on the differential inputs duplicating resources... or is there a way to get the single-ended clock for use by my own fabric logic?
Also, Is there a better description of the core vs reference clock somewhere; I find the ip documentation description lacking.
03-28-2017 05:37 AM