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petersk
Explorer
Explorer
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Registered: ‎07-29-2009

JESD204B reference clock

I'm having a hard time with the JESD204B core in understanding the way clocks are used.  I have my own Verilog code running with what should be the same clock speed as the JESD204B reference clock. Can I use the JESD input clock?  The problem is that the core takes a differential input and then uses "clocking support" with an MMCM and BUFG internally to provide the clock to the core. I therefore can't really use the clock externally without adding my own MMCM and BUFG on the differential inputs duplicating resources... or is there a way to get the single-ended clock for use by my own fabric logic?

Also, Is there a better description of the core vs reference clock somewhere; I find the ip documentation description lacking.

Regards,
Kurt

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venkata
Moderator
Moderator
3,511 Views
Registered: ‎02-16-2010

Can you check the "shared logic in the example" option? Check if the clocking support module is brought outside the IP so that you have access to the GT reference clock.
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petersk
Explorer
Explorer
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Registered: ‎07-29-2009

I saw in one of the manuals that "tx_core_clk_out" will probably be the right thing to use. Is that phase aligned using an MCMM to the refclk_p?
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