01-17-2009 09:47 AM - edited 01-17-2009 09:55 AM
Is this an academic exercise?
If not, the practical answer is an emphatic no. The difficulties for most people will exceed any benefit.
If so, clearly it is functionally possible:
Is it a good idea? Absolutely not. The control you will need over the routing and choice of LUT input to maintain required timing would be extremely difficult for most people. And the timing tools are certainly not designed to analyze this.
There is already an abundance of FFs in the FPGA - most users likely run out of other resources before they run out of FFs.
The slice is designed so you just worry about the functional usage of the FFs and proper timing constraints. An FPGA is not an ASIC with transistor level design tools and timing modeling.
== even on an ASIC flow, there are existing libraries for designers to leverage.
01-17-2009 06:36 PM
If you mean build a flip-flop from gates - an exercise in asynchronous sequential logic design,
I would agree with timpe. However if you're looking for more flip-flops and have extra LUT's,
you can get a lot of flip-flops using the SRL16 instead of the generic LUT resources. The
only thing you lose is the asynchronous set and reset capability of the flip-flop. XST will
infer SRL16's where you meet the requirements - no asynchronous set/reset and for multiple
stages in the same SRL no other logic between stages.