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jamesjisun
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Registered: ‎08-13-2011

LUT implemented inverter is really an inverter on the FPGA?

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Hi there,

 

When I click an LUT in the schematic view and it shows an inverter as expected. But I am wondering if it is implemented on Xilinx FPGA by an inverter or actually the schematic view is not equivalent to the truth on the FPGA?

 

Thanks,

J

lut.png
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ywu
Xilinx Employee
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Registered: ‎11-28-2007

The LUT1_1 primitive will be implemented in a LUT4 and LUT6 depending on the device family. As the name LUT (look up table) indicates, it is a 16-to-1 (LUT4) or 64-to-1 (LUT6) memory with the logic inputs as the address. LUT can handle any arbitrary logic function with 4 inputs (LUT4) or 6 inputs (LUT6) by way of looking up the memory to generate the output.


@jamesjisun wrote:

Hi there,

 

When I click an LUT in the schematic view and it shows an inverter as expected. But I am wondering if it is implemented on Xilinx FPGA by an inverter or actually the schematic view is not equivalent to the truth on the FPGA?

 

Thanks,

J




Cheers,
Jim

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joelby
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Registered: ‎10-05-2010

No, it will probably be implemented using a LUT on the FPGA. It's generally best not to think of FPGA designs in terms of primitive digital logic gates!

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eteam00
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Registered: ‎07-21-2009

No, it [inverter] will probably be implemented using a LUT on the FPGA.

 

Agreed, but not always.  For instance, clock polarity selects are often muxes or inverters buried within a larger primitive.

 

It's generally best not to think of FPGA designs in terms of primitive digital logic gates!

 

Agreed.  Sounds like an academic study project (see another recent thread wanting to compare long lines vs. short lines).

 

-- Bob Elkind

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joelby
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Agreed, but not always.  For instance, clock polarity selects are often muxes or inverters buried within a larger primitive.


Yeah, I was going to add that caveat, but then I thought that the selection is programmable, so if you squint it's still a bit like a lookup table. I agree that the underlying implementation would probably be decidedly more invertery in these cases.

 

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eteam00
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Yeah, I was going to add that caveat, but then I thought that the selection is programmable, so if you squint it's still a bit like a lookup table. I agree that the underlying implementation would probably be decidedly more invertery in these cases.

 

As this inquiry is most likely for an academic paper, nothing less than a device-level description of the entire FPGA will suffice.  We can count the minutes until Austin Lesea comes to the rescue.

 

-- Bob Elkind

SIGNATURE:
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2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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joelby
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I found some great information on how selectable inverters are implemented - perhaps these are similar to the ones used by clock polarity selects.

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jamesjisun
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Registered: ‎08-13-2011

Hi,

 

Thanks for the answers from both of you. I think LUT is just a name, and it should be consisted of several gates. And I am confusing if a simple inverter is enough, the LUT should shrink to be an inverter instead of a complicated combinational logic. This is also from the power issue.

 

Any idea on how a LUT is composed of?

 

Cheers,

J

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joelby
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Registered: ‎10-05-2010

A LUT is essentially a bit of memory with a number of inputs and outputs and consists of a whole stack of gates. Have a read of, for example, the Spartan-6 CLB User Guide.

 

These are fixed in hardware. It is their reconfigurability that allows them to emulate inverters and other gates. The LUT might 'functionally' reduce to an inverter, but the underlying implementation can't be changed.

 

 

 

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ywu
Xilinx Employee
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Registered: ‎11-28-2007

The LUT1_1 primitive will be implemented in a LUT4 and LUT6 depending on the device family. As the name LUT (look up table) indicates, it is a 16-to-1 (LUT4) or 64-to-1 (LUT6) memory with the logic inputs as the address. LUT can handle any arbitrary logic function with 4 inputs (LUT4) or 6 inputs (LUT6) by way of looking up the memory to generate the output.


@jamesjisun wrote:

Hi there,

 

When I click an LUT in the schematic view and it shows an inverter as expected. But I am wondering if it is implemented on Xilinx FPGA by an inverter or actually the schematic view is not equivalent to the truth on the FPGA?

 

Thanks,

J




Cheers,
Jim

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