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wuchy143
Observer
Observer
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Registered: ‎05-25-2010

LUT's and CLB's

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HI All,

 

Couple noob questions:

 

1. I understand that the basic building block for fpga's are the LUT's which consist of a LUT, DFF and a 2:1 mux in case you want to bypass the DFF. Exactly what is in the LUT? how do the four inputs get the desired result? 

 

2. I"m a little confused as to what a CLB is. Is it just a collection of LUT's?

 

Responses much appreciated

 

-mike

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sonicwave
Explorer
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Registered: ‎11-26-2008

A LUT (or LookUp-Table) is basically just a small memory. A 4-input, 1-output LUT, can generate any 4-input boolean function (AND / OR / XOR / NOT / combinations of these / etc). When you configure the FPGA, you also configure the contents of the LUT, and thus the function that you want it to perform.

 

A CLB (Configurable Logic Block) basically consists of a LUT, a FlipFlop and multiplexer. In reality, a CLB is a bit more complex though. In a Spartan3 for instance, a CLB holds four slices, where each slice contains a LUT, a FlipFlop, and a number of multiplexers and various routing resources. You can have a look at the Spartan3 family datasheet (DS099) - from page 22, there's a section titled "CLB overview".

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sonicwave
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Registered: ‎11-26-2008

A LUT (or LookUp-Table) is basically just a small memory. A 4-input, 1-output LUT, can generate any 4-input boolean function (AND / OR / XOR / NOT / combinations of these / etc). When you configure the FPGA, you also configure the contents of the LUT, and thus the function that you want it to perform.

 

A CLB (Configurable Logic Block) basically consists of a LUT, a FlipFlop and multiplexer. In reality, a CLB is a bit more complex though. In a Spartan3 for instance, a CLB holds four slices, where each slice contains a LUT, a FlipFlop, and a number of multiplexers and various routing resources. You can have a look at the Spartan3 family datasheet (DS099) - from page 22, there's a section titled "CLB overview".

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wuchy143
Observer
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Registered: ‎05-25-2010

sonicwave thanks for such a good response. makes sense!

 

The only thing which I"m a little fuzzy on is when/where/how the LUT gets "configured" to do the 4 different boolean functions. I understand that the fpga is programmed into it's CCL's(CMOS configuration latches) when it's powered up. So does that information itself change how the LUT's will respond given certain inputs?

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sonicwave
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Registered: ‎11-26-2008

I must admit that I'm not completely sure about how the LUTs are actually implemented, but according to the datasheet they are RAM-based. So I guess they are configured just as you would otherwise store data into any other kind of RAM module. The four inputs just act as an address bus, addressing one of 16 (2^4) stored bits - thus being able to emulate any four-input boolean function.

 

If anyone else has a better understanding of the inside "mechanics", feel free to elaborate;)

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mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

A LUT, Look Up Table, has the same functionality as a ROM.  Each of the inputs is essentially an address in to a 16 deep by 1 bit ROM.  An example of this is shown below:

 

I3 I2 I1 I0 | State

------------+------

 0  0  0  0 |  0

 0  0  0  1 |  0

 0  0  1  0 |  0

 0  0  1  1 |  1

 0  1  0  0 |  0

 0  1  0  1 |  0

 0  1  1  0 |  0

 0  1  1  1 |  1

 1  0  0  0 |  0

 1  0  0  1 |  0

 1  0  1  0 |  0

 1  0  1  1 |  1

 1  1  0  0 |  1

 1  1  0  1 |  1

 1  1  1  0 |  1

 1  1  1  1 |  1

 

A ROM table isn't very useful to determine the function, but if transform this into a 2x2 Karnaugh map like this

 

 I3 \ I1

  I2 \ I0      

      \  0 0 | 0 1 | 1 1 | 0 1 |  

 ------+-----+-----+-----+-----+

   0 0 |  0  |  0  |  1  |  0  |

 ------+-----+-----+-----+-----+

   0 1 |  0  |  0  |  1  |  0  |

 ------+-----+-----+-----+-----+

   1 1 |  1  |  1  |  1  |  1  |

 ------+-----+-----+-----+-----+

   1 0 |  0  |  0  |  1  |  0  |

 ------+-----+-----+-----+-----+

 

it should be easy to see that the function is (I0 AND I1) OR (I2 and I3)

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
wuchy143
Observer
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Registered: ‎05-25-2010

Thanks guys/gals. This was very helpfull!!!!

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

You may also find these useful background for the alternate operating modes for the LUTs in the SLICEM blocks:

http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf (Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs)
http://www.xilinx.com/support/documentation/application_notes/xapp464.pdf (Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs)

There are other useful white papers as well:

http://www.xilinx.com/support/documentation/white_papers/wp309.pdf (Targeting and Retargeting Guide for Spartan-6 FPGAs)

http://www.xilinx.com/support/documentation/white_papers/wp248.pdf (Retargeting Guidelines for Virtex-5 FPGAs)
http://www.xilinx.com/support/documentation/white_papers/wp284.pdf (Advantages of the Virtex-5 FPGA 6-Input LUT Architecture)
http://www.xilinx.com/support/documentation/white_papers/wp272.pdf (Get Smart About Reset: Think Local, Not Global)
http://www.xilinx.com/support/documentation/white_papers/wp275.pdf (Get your Priorities Right – Make your Design Up to 50% Smaller)
http://www.xilinx.com/support/documentation/white_papers/wp231.pdf (HDL Coding Practices to Accelerate Design Performance)

 

bt

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spochiraju
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Registered: ‎04-06-2014

why is output of LUT always 1 bit wide? if there is 2 x2 multiplier, should not output me 4 bits wide?

 

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bassman59
Historian
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Registered: ‎02-25-2008

@spochiraju wrote:

why is output of LUT always 1 bit wide? if there is 2 x2 multiplier, should not output me 4 bits wide?

 


Why is it one bit wide? Because it is a function generator that was designed to have a single bit output.

 

A 2 x 2 mutliplier requires more than one LUT, because as you note, the output of a LUT is one bit wide.

----------------------------Yes, I do this for a living.