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rudy
Explorer
Explorer
5,269 Views
Registered: ‎04-29-2010

LUT6/LUT5

 Hi,

 

I am working with a Virtex 5 device.  I would like to once take the logical OR of 5 bits, and the other time, take the logical AND of these 5 bits.

I know that in Virtex 5, LUT6 architecture is such that we can perform either 6 Boolean operation on 6 independent inputs and produce one output, Or, that we can use the LUT6 such that we use only 5 bits (in a shared fashion) to produce 2 sets of independent outputs, with each being a different Boolean operation on the 5 input bits. 

So, I believe that with just one LU6, I am able to perform both logical OR and logical AND of a 5 bit input.

But here is my question?

How do I know that how the synthesis tool (XST) will interpret this operation? 

I know that I have an option of instantiating a LUT6 the way that I want, but I would like to avoid the instantiation, and let the tool infer my desired operation. 

Let's say that II have something like the following line, in my vhdl code:

 

X <= x(0) or x(1) or x(2) or x(3) or x(4) 

Y <= x(0) and x(1) and x(2) and x(3) and x(4)

 

How do I know if XST will use just one LUT6 to perform this operation, or it will in fact use two LUT6 to perform the above operation?

In my design, I am very resource limited, and I have to take all the precautions to make sure I am using as less resources as possible.

Any idea as far as what I can do on my behalf (except instantiation) to make sure that the tool will perform the above operation using only one LUT6?

 

Thanks in advance, 

Rudy 

 

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2 Replies
eteam00
Professor
Professor
5,262 Views
Registered: ‎07-21-2009

This recent thread might be helpful for you.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bassman59
Historian
Historian
5,241 Views
Registered: ‎02-25-2008


@rudy wrote:

 Hi,

 

I am working with a Virtex 5 device.  I would like to once take the logical OR of 5 bits, and the other time, take the logical AND of these 5 bits.

I know that in Virtex 5, LUT6 architecture is such that we can perform either 6 Boolean operation on 6 independent inputs and produce one output, Or, that we can use the LUT6 such that we use only 5 bits (in a shared fashion) to produce 2 sets of independent outputs, with each being a different Boolean operation on the 5 input bits. 

So, I believe that with just one LU6, I am able to perform both logical OR and logical AND of a 5 bit input.

But here is my question?

How do I know that how the synthesis tool (XST) will interpret this operation? 

I know that I have an option of instantiating a LUT6 the way that I want, but I would like to avoid the instantiation, and let the tool infer my desired operation. 

Let's say that II have something like the following line, in my vhdl code:

 

X <= x(0) or x(1) or x(2) or x(3) or x(4) 

Y <= x(0) and x(1) and x(2) and x(3) and x(4)

 

How do I know if XST will use just one LUT6 to perform this operation, or it will in fact use two LUT6 to perform the above operation?

In my design, I am very resource limited, and I have to take all the precautions to make sure I am using as less resources as possible.

Any idea as far as what I can do on my behalf (except instantiation) to make sure that the tool will perform the above operation using only one LUT6?

 

Thanks in advance, 

Rudy 

 


Why not just write the code in a way that makes sense to a human, and let the synthesizer sort it out? As long as you meet your timing constraints, how the tools choose to build the logic is irrelevant.

----------------------------Yes, I do this for a living.
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