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Visitor abhilash_r
Visitor
227 Views
Registered: ‎04-01-2019

LVDS passthrough CPLD/FPGA

Hi, 

I am planning to use CPLD/FPGA to passthrough LVDS signals. Signal consist of 1 clock pair and 3 data pair. I think the recommended method is to terminate LVDS, then propage it and in the output again convert it to LVDS. I can't introduce any skew between the singals. Is it possible to to this with FPGA/CPLD with some routing constrains or soemthing.

Thanks in advance

 

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Scholar drjohnsmith
Scholar
211 Views
Registered: ‎07-09-2009

Re: LVDS passthrough CPLD/FPGA

"without skew" , not possible.

If they are uni directional signals, and can be registered, then receiving then in the FPGA, registering and then sending on would be the best you could do to minimise skew,

 

 

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