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9,001 Views
Registered: ‎04-24-2010

Large multiplexers

Hello,

 

I have to implement a big multiplexer of approximately 100 signals of 16 bits each. Apart from the typical ways to implement this kind of structures ("case-when", "with-select", "if-then" or "when-else"), I also found that it could be advantageous to use AND-OR structures. Does anyone know something about this?  

 

I would also like to know how to declare all the input signals in a VHDL entity.

 

Thank you,

 

Victor M.

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Xilinx Employee
Xilinx Employee
8,982 Views
Registered: ‎01-03-2008

Your terms "case-when", "with-select", "if-then" or "when-else" are HDL behavioral ways to describe a multiplexer and an "AND-OR structure": is a standard gate level implementation of a multiplexer.

 

The synthesizer will select an optimal gate level implementation (which in current Xilinx architectures will be a combination of LUTs and MUXF# combinations with the LUTs implemented as AND-OR equation  for your HDL functionality.

 

> I would also like to know how to declare all the input signals in a VHDL entity

 

This doesn't make any sense, unless you have no VHDL experience..  If you have no VHDL experience then I would suggest that you pick up a good VHDL book and start reading.

------Have you tried typing your question into Google? If not you should before posting.
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8,983 Views
Registered: ‎04-24-2010

In my last question I ask if is it possible to declare an array of std_logic_vector in the entity. Because otherwise I am forced to declare 100 different std_logic_vector inputs.

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Xilinx Employee
Xilinx Employee
8,977 Views
Registered: ‎01-03-2008

And what does your reference material or Google say about std_logic_vector arrays?

------Have you tried typing your question into Google? If not you should before posting.
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Historian
Historian
8,953 Views
Registered: ‎02-25-2008

 


@fpgasparatodos wrote:

In my last question I ask if is it possible to declare an array of std_logic_vector in the entity. Because otherwise I am forced to declare 100 different std_logic_vector inputs.


Did you follow Ed McGett's advice and purchase and study a good VHDL reference text?

 

----------------------------Yes, I do this for a living.
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8,943 Views
Registered: ‎04-24-2010

I have been reading about my problem, and I think that it may be solved by using a package that defines the array of std_logic_vector type. If you know other solution I will appreciate the suggestion.

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Historian
Historian
8,913 Views
Registered: ‎02-25-2008

 


@fpgasparatodos wrote:

I have been reading about my problem, and I think that it may be solved by using a package that defines the array of std_logic_vector type. If you know other solution I will appreciate the suggestion.


 

Uhhh, that package is called std_logic_1164, and is the same package that defines std_logic.

 

RIGHT NOW, go buy a copy of Peter Ashenden's "The Designer's Guide To VHDL." Do not continue until you've read the book.

----------------------------Yes, I do this for a living.
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8,905 Views
Registered: ‎04-24-2010

I think that you can reply more politely. Moreover if you know the solution and it is so easy, it takes only 30 seconds to write it. 

 

I have found that people use their own package (and I don't talk about std_logic_1164) to define the array of std_logic_vector type and then declare the input/output ports with this new data type:

 

http://objectmix.com/vhdl/396975-array-entity-declaration.html

http://www.velocityreviews.com/forums/t601398-passing-arrays-via-port-map.html

 

 

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Instructor
Instructor
8,899 Views
Registered: ‎07-21-2009

I don't think you have any standing to judge Bassman and his response.  This is an FPGA design support forum (not a HDL language teaching course forum), and you are asking questions which the most basic knowledge of VHDL would answer.

 

You came to this forum asking for help and advice, and the advice you were given was (in part) learn the language you're using for design.  You should consider accepting that advice rather than acting wounded because no-one handed your design to you on a silver platter.

 

The folks in this forum generally understand that if you don't understand the language basics, you are likely to have a never-ending series of roadblocks with which to contend.  These same folks are trying to convey to you that learning the language will help you understand and solve your original questions...  and make you a better designer, better equipped to fend for yourself.

 

You can take the advice or not, it's up to you.  Personally, I lose patience with folks who don't make an honest effort to help themselves and learn in the process.  I don't work for Xilinx, so don't take my comments to represent Xilinx' approach to customer support.  I'm not trying to be mean or insulting, but (I presume) you get paid to be a design engineer, and learning the tools is part of your job.

 

-- Bob Elkind

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Historian
Historian
8,862 Views
Registered: ‎02-25-2008

 


@fpgasparatodos wrote:

I think that you can reply more politely. Moreover if you know the solution and it is so easy, it takes only 30 seconds to write it. 

 

I have found that people use their own package (and I don't talk about std_logic_1164) to define the array of std_logic_vector type and then declare the input/output ports with this new data type:

 

http://objectmix.com/vhdl/396975-array-entity-declaration.html

http://www.velocityreviews.com/forums/t601398-passing-arrays-via-port-map.html

 

 


 

Those packages are talking about arrays of arrays, or more correctly, arrays of std_logic_vectors. They still need std_logic_1164 to declare both the std_logic and std_logic_vector types.

 

So I did give you the easy, and correct, answer. If you don't like the answer, that's your problem.

 

Thanks for playing, though.

----------------------------Yes, I do this for a living.
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