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Participant mionch
Participant
7,348 Views
Registered: ‎03-21-2013

Locked Synthesis

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I don't know what's happening... my process of Synthesis in PlanAhead locks without any message... It locks in this part:


Synthesizing Unit <memram>.
Related source file is "E:/SinteseSpeedUltimo/project_2.srcs/sources_1/imports/Desktop/memram.vhd".
WARNING:Xst:647 - Input <address<31:21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <address_write<31:21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

 

 

What's going on? How can I fix the problem if I don't know what's it?:??

 

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Guide avrumw
Guide
9,392 Views
Registered: ‎01-23-2009

Re: Locked Synthesis

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I see that you are trying to infer a large, initialized, byte writable RAM. Synthesis is VERY picky when it comes to RAMs, and byte writable RAMs are the worst. The format of the RTL code must be exactly write to infer the block RAM, otherwise it doesn't recognize it as a RAM and, instead, tries to generate it with an immense number of flip-flops - way more than the synthesis tool can really handle.

 

I have heard (and seen) cases where this happens, and synthesis runs for rediculously long periods of time before giving a totally useless result (since it consumes thousands of times the number of flip-flops that you have in the device). This is probably what is happening here.

 

(While I can't actually tell how big the RAM is supposed to be), this looks like a pretty large RAM. If the total RAM size is bigger than 128kbit, you might make the tools job easier by describing 4 separate byte wide RAMs (with independent write enables), instead of one larger byte writeble RAM. They will likely end up with the same implementation in the end (since it will take more than 4 block RAMs to implement them anyway). The tools are less picky about the structure of the code when the RAM does not have byte enables.

 

Also, make sure you look at the RAM templates available from ISE or Vivado (from the language templates - the little lightbulb). This will show you how to code the RAM so that the synthesis tool will be able to understand it.

 

Alternatively, instead of trying to infer the RAM (which is my preferred method), you can use CoreGen to generate the RAM. You can even provide an initialization file to the coregen generated RAM to get you initial values into it. I am not a VHDL expert, but I am concerned that your method of initializing the RAM  may be messing up the synthesis tool.


While I can't be certain this is the root of the problem, I have seen this before, so it is pretty likely...

 

Avrum

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9 Replies
Professor
Professor
7,333 Views
Registered: ‎08-14-2007

Re: Locked Synthesis

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You could try to leave this module out to make sure that it is the one causing the lock up.  It's always possible that synthesis got hung up after completing this module but before it output any other messages.

 

If this module is trying to describe a ver large memory, it's also possible that reducing the memory size will fix the lock up.  Have you determined that the memory actually fits your device?  Also have you checked if synthesis has really "locked up" and isn't just taking a very long time?  You could for example leave it running overnight to see if it completes.  In any case, a very large memory description could cause long synthesis run time or system memory overflow.

-- Gabor
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Teacher muzaffer
Teacher
7,327 Views
Registered: ‎03-31-2012

Re: Locked Synthesis

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have you checked if synthesis has really "locked up" and isn't just taking a very long time? 

 


I am pretty sure that's very difficult to decide ;-)

 

 

 

 

 

http://en.wikipedia.org/wiki/Halting_problem

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Xilinx Employee
Xilinx Employee
7,313 Views
Registered: ‎09-20-2012

Re: Locked Synthesis

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Hi,

Try the suggestions in this ar http://www.xilinx.com/support/answers/40377.html

If you are not able to narrow down the issue, post the test case so that we can have a look.

Thanks,
Deepika.
Thanks,
Deepika.
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Participant mionch
Participant
7,299 Views
Registered: ‎03-21-2013

Re: Locked Synthesis

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But it doesn't show any error =\

This time I let it run for 30 hours, and no message and got locked. 

I attached the run log file and my ram memory vhd. 

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Guide avrumw
Guide
9,393 Views
Registered: ‎01-23-2009

Re: Locked Synthesis

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I see that you are trying to infer a large, initialized, byte writable RAM. Synthesis is VERY picky when it comes to RAMs, and byte writable RAMs are the worst. The format of the RTL code must be exactly write to infer the block RAM, otherwise it doesn't recognize it as a RAM and, instead, tries to generate it with an immense number of flip-flops - way more than the synthesis tool can really handle.

 

I have heard (and seen) cases where this happens, and synthesis runs for rediculously long periods of time before giving a totally useless result (since it consumes thousands of times the number of flip-flops that you have in the device). This is probably what is happening here.

 

(While I can't actually tell how big the RAM is supposed to be), this looks like a pretty large RAM. If the total RAM size is bigger than 128kbit, you might make the tools job easier by describing 4 separate byte wide RAMs (with independent write enables), instead of one larger byte writeble RAM. They will likely end up with the same implementation in the end (since it will take more than 4 block RAMs to implement them anyway). The tools are less picky about the structure of the code when the RAM does not have byte enables.

 

Also, make sure you look at the RAM templates available from ISE or Vivado (from the language templates - the little lightbulb). This will show you how to code the RAM so that the synthesis tool will be able to understand it.

 

Alternatively, instead of trying to infer the RAM (which is my preferred method), you can use CoreGen to generate the RAM. You can even provide an initialization file to the coregen generated RAM to get you initial values into it. I am not a VHDL expert, but I am concerned that your method of initializing the RAM  may be messing up the synthesis tool.


While I can't be certain this is the root of the problem, I have seen this before, so it is pretty likely...

 

Avrum

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Participant mionch
Participant
7,253 Views
Registered: ‎03-21-2013

Re: Locked Synthesis

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Hi avrumw, I made what you said about using the coregen to generate an IP RAM... but I got another problem.... memory_initialization_radix can only have 16 bits... and my structure has instructions of 32 bits. How can I solve this??
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Professor
Professor
7,251 Views
Registered: ‎08-14-2007

Re: Locked Synthesis

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The memory initialization radix is the number base, 16 = hexadecimal.  It's not the number of bits in the word.  So if your data is in hexadecimal (0-9 A-F) then use 16 and make sure each entry has the appropriate number of digits to fill the actual word size of the RAM (RAM bit width / 4).

-- Gabor
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Participant mionch
Participant
7,246 Views
Registered: ‎03-21-2013

Re: Locked Synthesis

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Oh... my mistake. Sorry and thanks.
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Participant mionch
Participant
7,223 Views
Registered: ‎03-21-2013

Re: Locked Synthesis

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Many thanks avrumw !! You helped me a lot.
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