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Explorer
Explorer
5,206 Views
Registered: ‎08-23-2011

LogiCore IP clock generator v4.03A - GUI/core/compilation quesitons ...

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hi,

 

i am using xilinx ISE 14.1 and virtex6 device. I have a design that uses Logicore IP clock generator v4.30A and AXI CDMA v3.02A.

 

My questions regarding the Logicore IP blocks are -

 

for clock generator v4.03A, the data sheet says supported devices are virtex6 and sim tool is modelsim. however when i open the xilinx core generator GUI, i only see clocking wizard for virtex6 device. i donot see a clock generator core.  ..

1) in coregen, which core/GUI option generates or uses the clock generator library?

 

2) if i generate simulation libs for modelsim using compxlib command, will this core be generated? if so, by what name and in whcih folder should it be present? or do i need to do something special to generate this core seperately?

 

3) the xilinx document says - tested sim tool is modelsim. so does it mean that if i do a compxlib for vcs MX 2011, these cores will not be generated? or will i still be able to use these cores in vcs?

 

4) in case these cores will not be generated for vcs, then do i need to move some lib files manually into my vcs sim dir to simulate this core? is that feasible?

 

5) similarly, if i do a compxlib for modelsim, then the AXI CDMA core will be available as which file/folder name?

 

please let me know ...

 

thanks ...

 

z.

 

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Xilinx Employee
Xilinx Employee
8,807 Views
Registered: ‎07-31-2012

Re: LogiCore IP clock generator v4.03A - GUI/core/compilation quesitons ...

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1) in coregen, which core/GUI option generates or uses the clock generator library?

A: Are you planning to implement the clocks in XPS. Clock Generator and Clocking wizard are different. If you are working in ISE/Vivado without EDK, then you need to search for clocking wizard and not for clock generator. IF yo uare searching fo rthe clock generator then it is in the XPS tool.

 

2) if i generate simulation libs for modelsim using compxlib command, will this core be generated? if so, by what name and in whcih folder should it be present? or do i need to do something special to generate this core seperately?

A: Read same as above for this. however if you need modelsim then you need to compile libraries to use it. But compiling libraries is not a pre requisite for it to show up in the GUI.

 

3) the xilinx document says - tested sim tool is modelsim. so does it mean that if i do a compxlib for vcs MX 2011, these cores will not be generated? or will i still be able to use these cores in vcs?

A: Again answer same as above.

 

 

4) in case these cores will not be generated for vcs, then do i need to move some lib files manually into my vcs sim dir to simulate this core? is that feasible?

A: No, you just have to uupdate the modelsim.ini file with the generated ini file, which points to the location of the compiled libraries if you are using ISE.

 

5) similarly, if i do a compxlib for modelsim, then the AXI CDMA core will be available as which file/folder name?

No need to run compxlib for showing the cores. YOu need to search for these core in XPS and not ISE.

 

 

Hope i have answered your questions.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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3 Replies
Xilinx Employee
Xilinx Employee
8,808 Views
Registered: ‎07-31-2012

Re: LogiCore IP clock generator v4.03A - GUI/core/compilation quesitons ...

Jump to solution

1) in coregen, which core/GUI option generates or uses the clock generator library?

A: Are you planning to implement the clocks in XPS. Clock Generator and Clocking wizard are different. If you are working in ISE/Vivado without EDK, then you need to search for clocking wizard and not for clock generator. IF yo uare searching fo rthe clock generator then it is in the XPS tool.

 

2) if i generate simulation libs for modelsim using compxlib command, will this core be generated? if so, by what name and in whcih folder should it be present? or do i need to do something special to generate this core seperately?

A: Read same as above for this. however if you need modelsim then you need to compile libraries to use it. But compiling libraries is not a pre requisite for it to show up in the GUI.

 

3) the xilinx document says - tested sim tool is modelsim. so does it mean that if i do a compxlib for vcs MX 2011, these cores will not be generated? or will i still be able to use these cores in vcs?

A: Again answer same as above.

 

 

4) in case these cores will not be generated for vcs, then do i need to move some lib files manually into my vcs sim dir to simulate this core? is that feasible?

A: No, you just have to uupdate the modelsim.ini file with the generated ini file, which points to the location of the compiled libraries if you are using ISE.

 

5) similarly, if i do a compxlib for modelsim, then the AXI CDMA core will be available as which file/folder name?

No need to run compxlib for showing the cores. YOu need to search for these core in XPS and not ISE.

 

 

Hope i have answered your questions.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Explorer
Explorer
5,181 Views
Registered: ‎08-23-2011

Re: LogiCore IP clock generator v4.03A - GUI/core/compilation quesitons ...

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hi,

 

thanks for the reply - 

 

so i gather that clock_generator such as clock_generator_v4_03_a library is in XPS and not Xilinx ISE.

 

however the LogiCore doc mentions xilinx ISE as the design entry tool. so when it says "design entry tool", does it only mean for FPGA implementation? or does it have some other meaning?

 

z.

 

 

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Xilinx Employee
Xilinx Employee
5,169 Views
Registered: ‎07-31-2012

Re: LogiCore IP clock generator v4.03A - GUI/core/compilation quesitons ...

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Hi,

 

Its only with XPS. 

 

If you read the 2nd para of the clock generator datasheet - http://www.xilinx.com/support/documentation/ip_documentation/clock_generator/v4_03_a/clock_generator.pdf

 

you can find that "The generation algorithm is implemented in C++ programming language and currently it is only
integrated with the Hardware Platform Generator (PlatGen) and Simulation Generator (SimGen) EDK implementation tools."

 

To use in ISE, you need to use Clocking wizard.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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