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4,054 Views
Registered: ‎06-22-2011

MAXIMUM FREQUENCY UPTO WHICH MRCC,SRCC CAN BE CLOCKED

 

 Please let me know upto what frequency can SRCC,MRCC of VIRTEX-6 can be clocked.

 

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eteam00
Professor
Professor
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Registered: ‎07-21-2009

1.  Please do not ask such questions via private message.  Post your questions in the forums.

 

2.  This topic belongs in the VIRTEX forum.

 

3.  What are SRCC and MRCC?  SRCC and MRCC (Single-Region Clock Capable and Multi-Region Clock Capable) pins are not active circuits, they are specific pin groups on a package.  The buffer you choose for input clock signals determines the maximum clock frequency, not the package pin.  Check the Virtex-6 datasheet (DS152) for the operating range of the various clock buffers.  You will find this information in DS152 Tables 59, 60, 61, and 62.  For MMCM operating specifications, see DS152  Table 63.

 

The list of circuits which can be directly driven by MRCC/SRCC inputs may be found in UG362 Table A-1.

 

-- Bob Elkind

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bassman59
Historian
Historian
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Registered: ‎02-25-2008


@nikhil_km1989@yahoo.co.in wrote:

 

 Please let me know upto what frequency can SRCC,MRCC of VIRTEX-6 can be clocked.

 

 


RTFDS.

----------------------------Yes, I do this for a living.
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austin
Scholar
Scholar
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Registered: ‎02-27-2008

Gently,

Gently. We may know that this information is in the data sheet, but maybe they need to be shown where it appears?

Generally, performance in a FPGA device is limited by the VHDL or verilog they write, the constraints they used for the place and route, the IO pins they chose, along with many other factors. The maximum clock frequency is but one indicator of potential performance.

Until they learn this, (that FPGA devices are not like an Intel uP), they need to be taught.

Austin Lesea
Principal Engineer
Xilinx San Jose
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