cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
3,799 Views
Registered: ‎12-19-2013

Matrix Tranpose

Jump to solution

Hi to all,

 

I wrote matrix transpose program in vhdl environment , but i face one problem in that , it process only one data at a time, which is not my requirment , programe should take all entry simulataneously and provide transposed output in same manner , below is my code ...

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.typedef.all;

entity Matrix_Transpose is
Port ( A_In : in Doublearray;
trans_signal : in std_logic;
clk : in std_logic;
trans_ack : out std_logic;
transMat: out Doublearray);
end Matrix_Transpose;

architecture behavioral of Matrix_Transpose is
begin

trans_process : process (clk,trans_signal)
begin
if(rising_edge(clk)) then
if (trans_signal='1') then
for i in 0 to 2 loop
for j in 0 to 2 loop

transMat(i,j)<=A_In(j,i);


end loop;
end loop;
trans_ack<='1';
else
trans_ack<='0';
end if;
end if;
end process;

end behavioral;

 

 

package work.typedef declares single and double array type....

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
4,704 Views
Registered: ‎07-11-2011

Hi,

 

It worked for me with little changes in your for loop increment, you have declared 4 X4 matrix but assigning only 3 X3.

Aalso the order of for loop making difference.

 

You can see that outout is available as soon as trans_ack is asserted.

Attached the project along with tb for your reference.

 

 

matrix.png

 

 

Hope this helps.

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
3,789 Views
Registered: ‎07-11-2011

Hi,

 

Do you mean one element of A_in is copied to one element of  transMat at a time and the for loops are not incrementing in one clock ?

 

Can you show your double array declaration, test bench for trans_signal generation, how the input matrix is filled and simulation waveforms ?

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Highlighted
Visitor
Visitor
3,785 Views
Registered: ‎12-19-2013

exactly .. it accept only one element at a time

 and here is my double array declaration declared inside mydef package...

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package Typedef is


type DoubleDarray is
array(0 to 3, 0 to 3) of std_logic_vector(7 downto 0);
type SingleDarray is
array(0 to 3) of std_logic_vector(7 downto 0);
end package Typedef;

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
4,705 Views
Registered: ‎07-11-2011

Hi,

 

It worked for me with little changes in your for loop increment, you have declared 4 X4 matrix but assigning only 3 X3.

Aalso the order of for loop making difference.

 

You can see that outout is available as soon as trans_ack is asserted.

Attached the project along with tb for your reference.

 

 

matrix.png

 

 

Hope this helps.

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

0 Kudos