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Registered: ‎01-28-2013

Maximum Clock capable Input pins



I'm working on a design with ZynQ Z030/45 676pin package. This package has five banks and I get 20 clock capable inputs.


Now, I have 26 clocks (25MHz, single ended) coming into the device and these clocks will be used to capture/ send data in relation to them. So I need a clock dedicated route.


I seemed to have run into a wall here. The reason for bringing it to forum is to make sure my understanding is right and if so, if someone could provide a suggestion/ solution?



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4 Replies
Registered: ‎02-27-2008



The clock capable inputs are designed such that the delay and skew is well known, and the tools will use them for global and regional clock sources.


Any input pin may have a signal on it, and that signal may be a 'clock'.  At 25 MHz, that is a 40ns period, so timing should not be critical.  Thus you may use a regular input as long as timing is met (setup and hold times).  Some floor-planning (manual placement) may be needed, and you may have to look carefully at the verbose (complete) timing report and check that everything is OK.


It sounds like a very odd design (with so many clocks of the same frequency).  I would also be careful of clock domain crossings with so many clocks.  You may need FIFO's or synchronizers to pass data from one clock domain to another.


Constraints on the timing will also be critical to get correct:  ISE and Vivado treat clocks very differently, so for whatever you are using, read it over (applying clock and timing constraints, dealing with related, and unrelated clocks, and clock crossings).



Austin Lesea
Principal Engineer
Xilinx San Jose
Registered: ‎01-28-2013

Okay. I wanted to keep things simple. Looks like there is no other option.


I'm using a chip with such an interface and I have many of those chips to multiply the funtionality. I cannot do much about it.


Yep, I'll use fifos and synchronizers. 


Thanks for your suggestions.

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Registered: ‎07-21-2009

Austin is leading you in the right direction.


Let's assume you have a 100MHz system clock.  Using IDDR blocks, you have 5nS intervals at which you can sample input data (using both edges of the 100MHz clock).


Sample all of the data/clock groups with IDDR blocks, constantly.  Using edge detection logic to detect the rising edges of the clocks, use the "edge detected" events to select which samples of the input data (which edge, and which 100 MHz clock cycle) to accept as 'valid'.  The net result is that you have a single clock in your system rather than many -- the clock inputs from the external devices are used as data valid strobes rather than system clocks.  And this simplifies the overall design greatly -- no clock domain crossings.


Does this make sense?  If you have good (consistent and predictable) alignment of data to accompanying clock, you should have no trouble picking valid data (with 5nS resolution) from a 20nS window of valid data, at a 25MHz (40 nS cycle) rate.


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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2012

Hope you got good answers from previous posts. Also refer the below link document for complete details of cloking usage.


Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

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