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Visitor jmca
Visitor
10,301 Views
Registered: ‎02-29-2012

Metastability , double flopping and timing constraints.

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Hello:

 

I'm just having a time reviewing about constraining & timing issues.

 

After having checked Chapter 6  (Clock Domains) of  Advanced FPGA Design (Architecture, Implementation, and Optimization) of Steve Kilts I found a quote, referring to double flopping re-synchronization technique  that makes me think:

 

" Timing analysis should ignore the first resynchronization flip-flop and ensure that the timing between the synchronization flip-flops themselves is minimized".

 

Could someone provide an explanation to this? 

 

I just think that the implementation tools should ensure that there is enough timing between the synch flops to leave the potentially metastable output of the first one settle before being captured by the second one,  but I don't know how this fits with what the author says.

 

Regards,

 

Jose

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Teacher eteam00
Teacher
13,574 Views
Registered: ‎07-21-2009

Re: Metastability , double flopping and timing constraints.

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FF1 is sampled at time 0

FF2 is sampled at time 0+TnS, where TnS is clock period.

 

With 0nS interconnect delay between FF1 and FF2, FF1 output has time TnS to settle from metastable state before being sampled at FF2.

 

With 10nS interconnect delay between FF1 and FF2, FF1 output has time [T-10] nS to settle from metastable state before being sampled at FF2.

 

I left out a few details, but you get the idea.  Less time to settle from metastable state means higher failure rate at FF2.

 

-- Bob Elkind

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Teacher eteam00
Teacher
10,296 Views
Registered: ‎07-21-2009

Re: Metastability , double flopping and timing constraints.

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" Timing analysis should ignore the first resynchronization flip-flop and ensure that the timing between the synchronization flip-flops themselves is minimized".

 

Could someone provide an explanation to this?

 

I'll try.

 

At the first FF, it is assumed that no degree of layout or path delay control can ensure that setup and hold time (with respect to the clock) will be met.  The very nature of asynchronous inputs is that the setup and hold time is guaranteed to not be met, on occasion, and will be unaffected by path delays to the FF input.  Hence the exclusion of the first FF from timing analysis.  Such timing analysis is meaningless.

 

With a synchronising FF, it is assumed that a metastable condition will occur at the FF output.  The rate at which metastable conditions occur is determined by a number of factors (which are beyond the scope of this post).  These are matters of fundamental principles.  Part of these fundamental principles is that not only will metastable conditions occur, but the duration of a metastable condition will vary.  A metastable condition will -- occasionally -- persist long enough so that the FF output level will not "settle" in time to satisfy the setup time (to clock) at the second stage (FF) of the synchroniser.  In other words, a 2-stage synchroniser has a non-zero failure rate.

 

By minimising the propagation delay from the output of the first synchroniser stage to the input of the second stage, the failure rate of the 2-stage synchroniser will be dramatically reduced.  By the same token, increasing the delay between the two stages (with long interconnect, for example) will dramatically increase the failure rate of the 2-stage synchroniser.  This is the reason for minimising "the timing between the synchronisation FFs".

 

In practice, the gain of modern FPGA input buffers and registers is so high that the failure rate of a 1-stage synchroniser is quite low -- low enough to satisfy the requirements of many FPGA designs and/or FPGA designers.

 

Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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Visitor jmca
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10,291 Views
Registered: ‎02-29-2012

Re: Metastability , double flopping and timing constraints.

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Hi again, 

 

First part of explanation (concerning the exclusion of the first flip flop from the timing analysis) is understood.

 

But I'm having problems to visualize how minimizing the propagation delay between the two flip flops helps in avoiding metastatility. For a given situation in which the first FF output is metastable for Tm  time , placing the second FF closer would mean having more probability of sampling the signal while is metastable. 

 

I know that my reasoning is wrong , any help with this would be welcome.

 

Thanks

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Teacher eteam00
Teacher
13,575 Views
Registered: ‎07-21-2009

Re: Metastability , double flopping and timing constraints.

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FF1 is sampled at time 0

FF2 is sampled at time 0+TnS, where TnS is clock period.

 

With 0nS interconnect delay between FF1 and FF2, FF1 output has time TnS to settle from metastable state before being sampled at FF2.

 

With 10nS interconnect delay between FF1 and FF2, FF1 output has time [T-10] nS to settle from metastable state before being sampled at FF2.

 

I left out a few details, but you get the idea.  Less time to settle from metastable state means higher failure rate at FF2.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor jmca
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Registered: ‎02-29-2012

Re: Metastability , double flopping and timing constraints.

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Sure. Now I got the picture. It's good to have found that piece of information in S.Kilts book.

 

Thanks,

 

Jose

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Instructor
Instructor
10,271 Views
Registered: ‎08-14-2007

Re: Metastability , double flopping and timing constraints.

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To put some of this in the jargon of the timing analyzer, what you want is lots

of slack in the path from FF1 to FF2.  Slack is defined as the requirement

minus the actual path delay.  Chances of a metastable state exceeding the

slack time goes down very fast as the slack time increases.  You can use

a FROM : TO style constraint to require slack in the path berween flops, or

you can use RLOC constraints to keep the two flops together, making the

routing delays small.

 

-- Gabor

-- Gabor
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Visitor grpasche
Visitor
8,960 Views
Registered: ‎07-30-2013

Re: Metastability , double flopping and timing constraints.

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I read your explanation about the metastability, but I have questions:

 

I use a CPLD XC95144.

I want to synchronize with the CLK_IN's rising edge a asynchrone input signal (AS_IN). I think use a Flopping.

 

If I use a double flopping in the CPLD, the phenomenon of metastability decreases ?

 

If yes, have you an example in VHDL ?

Thank you for your answer

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