01-07-2013 08:20 PM
I am trying to follow a sample, but when export Hardware Design To SDK with Bitstream, it gives error. Seems the cystal clock not correct.
Any suggestion, thanks.
01-08-2013 04:28 AM
Your UCF states that the frequency of the input clock is 75MHz - does this match your hardware?
Neither your screenshots nor your messages show what the desired frequency output from your clock generator module is. What is the frequency of CLKOUT0?
01-08-2013 10:01 PM
The schematic for your project indicates that the input clock is 200MHz and the output clock is 75MHz. Is this what you want?
Your UCF indicates (especially to the tools) that your input clock is 75MHz - clearly a mismatch from your schematic.
What is it that you are actually trying to achieve?