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Newbie rmain_emb
Newbie
3,882 Views
Registered: ‎05-02-2012

Migrating from Actel APA600 to Xilinx FPGA

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I've been asked to recomend a suitable target to migrate from an Actel APA600 to a Xilinx FPGA product. The APA600 is in a PQ208 package, so IO requirement is pretty tame. The design is pure logic (there is no need of DSPs or high speed digtial IOs, embedded MACs, etc. ).

 

Can I assume Xilinx "Logic Cells" are roughly equivalent to Actel "Tiles"?

If so, the APA600 has 600,000 "Tiles", so I'd be looking at something like a Virtex-6 LXT, maybe XC6VLX550T, even though the pin count is WAY excessive (840 or 1200)?

 

Thanks,

R. Main

 

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Instructor
Instructor
4,806 Views
Registered: ‎08-14-2007

Re: Migrating from Actel APA600 to Xilinx FPGA

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The Spartan 6 LX25 should be a safe bet for logic capacity.  Perhaps you should check other

requirements like I/O standards (Spartan 6 supports a variety of standards up to 3.3V), and

speed.

 

Depending on your LUT vs flip-flop usage, it is likely that you could fit the design in a smaller

part.  You might want to try using the ISE webpack to see how your design synthesizes into

Spartan 6 LUTs and flip-flops.  Of course, how easy this is depends on how much you made

use of Actel-specific library elements.  A pure HDL design should port fairly easily.  Be careful

when using the "Logic Cells" numbers in the Spartan 6 Family Overview.  The actual number

of 6-input LUT's is smaller than the Logic Cells number, but there are twice as many flip-flops

as LUT's.  So going from a more standard 4-LUT+Flop architecture is not a one-to-one

conversion to logic cells.

 

-- Gabor

-- Gabor
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Newbie rmain_emb
Newbie
3,878 Views
Registered: ‎05-02-2012

Re: Migrating from Actel APA600 to Xilinx FPGA

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Sorry, the APA600 has 600,000 GATES, or 21,504 "Tiles".

If Tiles = Flip Flops, then the Spartan 6 LX would work, maybe a XC6LSX25?

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Instructor
Instructor
4,807 Views
Registered: ‎08-14-2007

Re: Migrating from Actel APA600 to Xilinx FPGA

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The Spartan 6 LX25 should be a safe bet for logic capacity.  Perhaps you should check other

requirements like I/O standards (Spartan 6 supports a variety of standards up to 3.3V), and

speed.

 

Depending on your LUT vs flip-flop usage, it is likely that you could fit the design in a smaller

part.  You might want to try using the ISE webpack to see how your design synthesizes into

Spartan 6 LUTs and flip-flops.  Of course, how easy this is depends on how much you made

use of Actel-specific library elements.  A pure HDL design should port fairly easily.  Be careful

when using the "Logic Cells" numbers in the Spartan 6 Family Overview.  The actual number

of 6-input LUT's is smaller than the Logic Cells number, but there are twice as many flip-flops

as LUT's.  So going from a more standard 4-LUT+Flop architecture is not a one-to-one

conversion to logic cells.

 

-- Gabor

-- Gabor
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Instructor
Instructor
3,866 Views
Registered: ‎08-14-2007

Re: Migrating from Actel APA600 to Xilinx FPGA

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I forgot to add that when you look at the device / package table in the S6 family overview,

the devices in the same package are footprint-compatible.  So you could for instance

start with a LX25 and if you find that your design fits in a LX16, then you could just replace

the chip without redesigning the board.  The device pinout tables list devices by

package, and indicate if some I/O pins are not available for certain footprint-compatible

parts.

 

-- Gabor

-- Gabor
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