cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
4,575 Views
Registered: ‎08-10-2009

Module Propogation Delays

I have simulated a verilog design that used some propagation delays like:     

 

and #20 (out, in1, in2);   (using #20 as 20 nanoseconds)

 

and the simulation works well. Now I want to implement these delays on a Spartan 3 board, but after going through the documentation I still can't get a handle on how to do that.

 

btw I'm using ISE 11 Web Pack

0 Kudos
4 Replies
Visitor
Visitor
4,574 Views
Registered: ‎08-10-2009

I'm thinking of just using a timer from the on board 50 MHz clock, but now I'm wondering how can I access that clock in verilog? And I'm assuming 1/50MHz = 20ns is the shortest delay I can get?

0 Kudos
Highlighted
Teacher
Teacher
4,551 Views
Registered: ‎07-09-2009

Hi

 

sorry dont know verilog, we speak the other language over here, 

 

but

 

You can not synthesise a delay into silicon. If you think of what the silicon would have to do, it would be a string of gates with a fixed delay.

 

You need to think syncronously, things happen on or because of a clock.

 

The Xilinx FPGA's have various DLL and PLL options, dependent upon the device , usefull amongst other things for making a faster internal clock.

 

You can also, if you are careful use both the rising and falling edge of a clcok, or even pahse shifts of a clock to get aparantly faster circuits. 

 

As for how to acces the timer.

 

When you make the timer, it will have a counting register, you access that.

 

Can I suggest you start with a few on line tutorials, they might break you in tho this sort of thinking.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
4,547 Views
Registered: ‎01-03-2008

Delay constructs in either VHDL or Verilog are not synthesizable into silicon they are intended for simulation purposes only.

 

If you have a clock that is 50 MHz (20ns) then you every register stage that is added will delay the signal by 1 clock period (20nS).

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
Highlighted
4,539 Views
Registered: ‎07-06-2008

#20 is a simulation construct...you can only have it working when in simulation software like ModelSim...if you read the stuff that the project navigator console prints out while synthesizing...if you something like #20 in your code it says that it is ignoring those delays...

 

If you want actual delays and dont want to use interrupts from timers (like, lets say in a MicroBlaze design) you can use something like this:

 

 

reg[25:0] count=0;

reg bit=0; 

 

always@(posedge clk)

begin

count<=count+1;

if (count==50000000)

begin

count<=0;

end

end

 

always@(negedge count[25])

begin

bit<=~bit;

end 

 

This will toggle the bit every 1 second on a 20ns (50MHz) clock like that on the Spartan 3 board...

 

 


 

0 Kudos