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Anonymous
Not applicable
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Multiple Clock Issues

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Let me start by saying I don't understand FPGA clocking resources as much as I'd like to. I've tried reading through whitepapers, but I always end up getting confused. I'm trying to implement the following code:

 

process(start)
begin
	if rising_edge(start) then
		if clk180 = '1' and clk270 = '1' then
			startQuarterPeriod <= "000";
		elsif clk90 = '1' and clk180 = '1' then
			startQuarterPeriod <= "001";
		elsif clk0 = '1' and clk90 = '1' then
			startQuarterPeriod <= "010";
		else -- clk0 = '1' and clk90 = '0' then
			startQuarterPeriod <= "011";
		end if;
	end if;
end process;

Signals clk0, clk90, clk180, and clk270 are generated by the DCM_ADV IP. Each signal is routed out through a BUFG. I'm trying to implement Nutt Interpolation in a TDC.The following warning and error occur during the Map process:

 

WARNING:Place:916 - Local congestion has been detected on component
   coarseCounter1/interpolator1/N11. There is a limitation that at most 2 global
   signals can drive non-clock pins per CLB. The placer has detected that
   component coarseCounter1/interpolator1/N11 has 3 non-clock pins driven by
   global signals. Placement will continue but note that this situation may lead
   to an unroutable situation. 

I found the component N11 using the RTL schematic viewer. It's a single input/output inverting gate (device and model = INV). I traced the different clock signals in the schematic, and I just don't see how it thinks there 3 signals driving it. Also, simple question, what are "pins" in this case? I've only thought of pins as the acutal, physical pins on the development board. What is a "non-clock pin"?

 

ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock
   IOB site. The clock IOB component <start> is placed at site <F34>. The clock
   IO site can use the fast path between the IO and the Clock buffer/GCLK if the
   IOB is placed in the master Clock IOB Site. If this sub optimal condition is
   acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
   in the .ucf file to demote this message to a WARNING and allow your design to
   continue. However, the use of this override is highly discouraged as it may
   lead to very poor timing results. It is recommended that this error condition
   be corrected in the design. A list of all the COMP.PINs used in this clock
   placement rule is listed below. These examples can be used directly in the
   .ucf file to override this clock rule.
   < NET "start" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

I don't understand why "start" is called a clock IOB component. It's not a clock, it is a input tied to one of the GPIO pins. When that pin goes high, a counter starts counting up from zero, as well as executes the code above.

 

Any suggestions? Of course this all simulated perfectly, but now I can't implement it...

 

 

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Guide
Guide
22,739 Views
Registered: ‎01-23-2009

The reply from @austin has a lot of good information on metastability, but I want to add one more thing.

 

Using a metastable signal inside a circuit can cause erroneous circuit behavior. For example, a metastable signal that is used as an input to a state machine can make the state machine go to a wrong, and possibly even illegal state. Depending on the design of the state machine, it may recover, producing only a momentary failure, or it may not, in which case your system has crashed.

 

Since you are using counters and "if" statements around this sampled start signal, all of these are possibilities. Rather than trying to analyze the behavior of the circuit in the presence of metastability, it is best to protect against it as much as possible. Even the snippet from the paper you quoted discusses that - the flip-flops past the original sample flip-flops are all for metastability resolution (and bringing the samples into the same clock domain). That being said, you still need constraints on the paths to make these valid metastability resolution circuits.

 

But that brings us to the main issue here...

 

There is only so much that we can help you with by answering specific questions. It seems that you have very little background in the design of digital circuits, synthesis, constraints, FPGAs, etc..., and the Xilinx forum is not the place to learn it. You need to take a class or read a book or find a mentor to teach you the basics before you embark upon a design...

 

Avrum

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Scholar
Scholar
13,785 Views
Registered: ‎02-27-2008

p,

 

If you wish to use the clock phases as output signals, you need to NOT use the BUFG.

 

Your code is not what I would use.


Instead, I would use the clock phase directly (as a clock).

 

Another way to do this properly for a synchronous system would be to Multiply the clock by 4, mand use that to drive a counter (or a state machine).  The state machine (decoded counter) outputs are used as clock enables to subsequent logic.  One  clock, everything else controlled by clock enables.

 

In the FPGA device, the simples state machine is a 1-hot state machine (4 DFF as a shift register fed back on itself).  The 4 DFF Q become the four enables.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Voyager
Voyager
13,779 Views
Registered: ‎04-21-2014

 


@Anonymous wrote:

 

 

I don't understand why "start" is called a clock IOB component. It's not a clock, it is a input tied to one of the GPIO pins. When that pin goes high, a counter starts counting up from zero, as well as executes the code above.

 

 


This is not an FPGA issue, but a synthesis issue. 

 

"start" is a clock.  You have coded it as such.  When the synthesizer sees the "rising_edge(any_signal_identifier)" in the pattern you have, it will code a register, and the "any_signal_identifier" will get connected to the clock input of a flip flop.

 

 


@Anonymous wrote:

 

 

Each signal is routed out through a BUFG. I'm trying to implement Nutt Interpolation in a TDC.The following warning and error occur during the Map process:

I found the component N11 using the RTL schematic viewer. It's a single input/output inverting gate (device and model = INV). I traced the different clock signals in the schematic, and I just don't see how it thinks there 3 signals driving it. Also, simple question, what are "pins" in this case? I've only thought of pins as the acutal, physical pins on the development board. What is a "non-clock pin"?

 

 


Vivado (for some reason) calls what normal people would think of pins or pads "ports" (though not consistently, e.g., some XDC constraints).  Pins are the (VHDL) ports of any module or primative in Vivado.  It is an unfortunate naming convention in my view--very confusing.

 

Regarding your error message, you CLK0, CLK90, CLK180 and CLK270 are being driven by BUFG's, but your code is using them in the combinatorial logic (LUTs).  Consequently, a path from a global net to general purpose routing needs to occur (generally not advisable).

 

I'm not sure what your frequencies are, but you may want to consider generating signals using a counter instead of using an MMCM_ADV.  You can still name them clk180 etc., but as long as you don't put them in a rising_edge(clk180), it will use general purpose routing.

 

You may want to consider VHDL training, or VHDL and Advanced VHDL (condensed) training.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Anonymous
Not applicable
13,736 Views

Austin, thank you so much for your reply! What do you mean you would use the clock phase directly? I also tried the code below, which didn't synthesize. Using four separate processes for the clock signals to try to control one signal (startQuarterPeriod) won't work either.

 

process(start)
begin
	if rising_edge(start) then
		startSig <= '1';
	end if;
end process;

process(clk0, clk90, clk180, clk270)
begin
	if startSig = '1' then
		if rising_edge(clk0) then
			startQuarterPeriod <= "000";
		end if;
		if rising_edge(clk90) then
			startQuarterPeriod <= "001";
		end if;
		if rising_edge(clk180) then
			startQuarterPeriod <= "010";
		end if;
		if rising_edge(clk270) then
			startQuarterPeriod <= "011";
		end if;
	end if;
end process;

 

I definitely understand multiplying the clock by 4. Currently I'm using the 100 MHz master clock, but the I hope to eventually use a 400 MHz clock with this interpolation design to achieve timing accuracy of 0.625 ns/LSB (1 / (4 * 400 MHz) = 1.6 GHz = 0.625 ns period).

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Anonymous
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13,734 Views

Morgan, I really appreciate your response! Thanks for the information! I just wish their training sessions weren't so expensive! :)

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Voyager
Voyager
13,701 Views
Registered: ‎04-21-2014

 


@Anonymous wrote:

Thanks for the information!  I just wish their training sessions weren't so expensive! :)


you're welcome peta...

 

Training seems expensive, but it pays for itself several times over when one is working on a funded project that is time critical, and the training will help avoid time sapping frustrations (meeting timing, using tools effectively, creating proper constraints, etc.). 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

I mean to not use the BUFG on 90, 180, and 270 DCM_ADV outputs.

 

It may be you have to instantiate the DCM_ADV primitive, and only use a BUFG for the CLOCK0 output.

 

That way you should be able to connect the signals as you originally tried, without getting the unreachable routing error.

 

Timing might be a bit odd (with/without BUFG will have different delay), but it should 'work.'

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Guide
Guide
13,628 Views
Registered: ‎01-23-2009

OK - let's take a step back...

 

Forget about VHDL for the moment - you have to think hardware.

 

Even a quick glance at the referenced paper clearly shows what the intent is - for Time to Digital Converers you want to get as accurate a measure of "time" as you can get.

 

As Austin recommended, the only reasonable way to do this in an FPGA is to sample the incoming signal (START) with as high a sample rate as you can. In any FPGA, there are physical limitations to the speed the internal clock can run at - these are determined by the maximum rate of the clock network inside the FPGA. Different FPGA families have different types of clock networks...

 

So, as an example, lets take an Artix-7 in the -1 speed-grade. The fastest frequency for a BUFG is 464MHz. Using simple sampling, you can get 464 million samples per second, and hence get a time resolution of 2.155ns.

 

However, for "good" TDC, this isn't fast enough - you want more precision. But you can't increase the clock rate past that point. So, you can consider sampling the data more than once during each clock phase. To do two samples per internal clock you simply use both edges of the internal clock and use double data-rate sampling using an IDDR; the IDDR is a specialized I/O cell specifically for sampling double data rate input signals. This can either be done using local inversion at the IDDR (which has some potential duty cycle issues at super high speeds) or use the IDDR_2CLK and sample on the clock and a 180 degree shifted version of the clock (which can be generated by an MMCM/PLL/DCM depending on the FPGA family). Doing this, you double the sampling rate, and effectively halve the resolution to 1.078ns. This will give you two samples each clock at 464MHz.

 

In the newer devices, you also have access to the ISERDES. Normally the ISERDES is used in SDR or DDR mode (the same as I described above). However, there is an additional mode called "Oversample Mode". In this case, you can sample an incoming signal using FOUR phases of the clock; CLK0, CLK90; CLK180; CLK270. These are generated by an MMCM or PLL (newer technologies) or a DCM (older technologies). In Oversample mode, you get 4 samples of the signal each clock; thus an effective sampling resolution of 539ps.

 

All of this seems to be described (pretty reasonably) in the referenced paper.

 

This is what the architectural capabilities of the FPGA are. Now you have to figure out how to use them.

 

Only the simplest "one sample per clock" can be inferred using VHDL or Verilog. All the fancier things need to be done by direct instantiation of the IDDR or IDDR_2CLK (for 2 samples per clock) or the ISERDES in oversample mode (for 4 samples per clock).

 

Avrum

 

 

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Guide
Guide
13,625 Views
Registered: ‎01-23-2009

Oh, and you can't forget metastability - by sampling the asynchronous signal this way, your IDDR or ISERDES will go metastable. So, before you can use this signal inside a state machine for determining its "time" you have to have it go through proper metastability resolution circuits. This will mean a number of back-to-back flip-flops on each signal to allow metastability to resolve. These flip-flops would have to have a special attribute (ASYNC_REG) set on them in Vivado, or would have to have a MAXDELAY time constraint set on the net between them in ISE. At high clock rates, you should consider 3 or even more sets of flip-flops for metastability.

 

Finally, your counters and comparators, etc... are all going to be very hard to get running at these high clock rates. You are probably going to want to run your design at a lower clock rate internally and treat multiple clock rates worth of samples in each of these lower clocks. So, for example, in the Artix-7 I used before, you would probably want to consider running your design not at 464MHz, but maybe at 232 and deal with the 4 samples from two consecutive 464MHz clocks at the same time.

 

Avrum

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Explorer
Explorer
13,437 Views
Registered: ‎06-25-2014

The code you have written does not describe fig 4 in your spec.

 

You need to think like this...

 

process(clk)
begin
if rising_edge(clk) then

 startstage1clk0 <= start; 

end if;

....

 

process(clk90)
begin
if rising_edge(clk90) then

startstage1clk90 <= start;

end if;

 

...etc

 

Then the second stage..

 

process(clk)
begin
if rising_edge(clk) then

startstage2clk0a <= startstage1clk0 ;

end if;

 

process(clk)
begin
if rising_edge(clk) then

startstage2clk0b <= startstage1clk90 ;

end if;

 

etc..

 

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Guide
Guide
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Registered: ‎01-23-2009

Be careful. If you try to infer the capture flip-flops in four seperate clocked processes (as @andrewlan suggests), then the four flip-flops will be inferred in the FPGA fabric - not in the IOB. When this happens the routing from the input buffer to the four capture flops is not guaranteed to be equal, which means that your samples won't be taken at exact 90 degree separations. Even with very careful constraints this can only be limited to a certain amount of skew - without proper constraints there can be even multiple nanoseconds of routing difference between the sampling flops.

 

The ISERDES in oversample mode will guarantee the samples are taken at 90 degree intervals to within the precision of the clock generation capabilities of the MMCM/PLL/DCM.

 

Avrum

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Anonymous
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a,

 

I'm currently using a Virtex-5, and according to the Libraries Guide, the ISERDES primitive for the 5-series FPGAs do not include an "oversampling mode".

 

From the article linked in my original post, the author included the following image and text: "Such samples feed other flip-flops to be synchronized to the same clock domain (clk) and avoid metastability."

 

d.PNG

 

You also said "At high clock rates, you should consider 3 or even more sets of flip-flops for metastability." Would you mind explaining why this is, or direct me to some further reading? Thank you so much for your help!

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Scholar
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Registered: ‎02-27-2008

p,

 

Metastability happens when you sample an asynchronous signal:  it cannot be avoided as the probability of it happening is always non-zero.

 

One adds more registers to reduce the probability.  But regardless of how many, it never goes away.

 

If it happens once in 100 years with one stage, the adding a stage takes it roughly to one in 10,000 years.  Three stages becomes 1 in 1,000,000 years.

 

What is the problem with metastability?  Well, it may not be a problem at all.  For example, a keyboard (like the one I am typing on) registers characters asynchronously.  If I type an 'a' but it is metastable, and it displays a '@' then we have a classic metastable event:  it got it wrong (if I recall my ASCII coide chart).  But it this case, no one cares.  People mis-type all the time.  As long as it is metastable less frequently than I mis-type, no one will ever notice.


So what happens if you get a wrong answer?  If you throw away bad data (do not include it at all), then you do not need to be obsessed with metastability.

 

Including metastable data even when averaging, or some other math operation will skew the result when it occurs.


If getting a wrong bit at the wrong time results in a dangerous condition (perhaps you are controlling a high speed train) then you have an architecture problem -- you need to re-design it so that it is no longer asynchronous, or in a way that it is no longer dangerous (as metatstability is never reduced to 0).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Guide
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Registered: ‎01-23-2009

The reply from @austin has a lot of good information on metastability, but I want to add one more thing.

 

Using a metastable signal inside a circuit can cause erroneous circuit behavior. For example, a metastable signal that is used as an input to a state machine can make the state machine go to a wrong, and possibly even illegal state. Depending on the design of the state machine, it may recover, producing only a momentary failure, or it may not, in which case your system has crashed.

 

Since you are using counters and "if" statements around this sampled start signal, all of these are possibilities. Rather than trying to analyze the behavior of the circuit in the presence of metastability, it is best to protect against it as much as possible. Even the snippet from the paper you quoted discusses that - the flip-flops past the original sample flip-flops are all for metastability resolution (and bringing the samples into the same clock domain). That being said, you still need constraints on the paths to make these valid metastability resolution circuits.

 

But that brings us to the main issue here...

 

There is only so much that we can help you with by answering specific questions. It seems that you have very little background in the design of digital circuits, synthesis, constraints, FPGAs, etc..., and the Xilinx forum is not the place to learn it. You need to take a class or read a book or find a mentor to teach you the basics before you embark upon a design...

 

Avrum

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Anonymous
Not applicable
12,350 Views

Well, you are right about the lack of background! I'm still in school, and unfortunately, we don't really have courses that get into the finer points of digital logic design. I sincerely appreciate both your and Austin's feedback. I guess it's time to hit the books! :)

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Voyager
Voyager
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Registered: ‎04-21-2014

Tell your professors to educate themselves so they can teach you.  :) 

 

This is taught very well at some universities. 

 

Other universities, not so much.

 

Anyway, don't be discouraged.  You can learn on your own, and perhaps educate some of your professors.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Explorer
Explorer
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Registered: ‎06-25-2014

I agree with avrums post and can imagine you getting pretty confused with talk of metastability or how to use the fabric blocks to reduce skew or operate in DDR to increase resolution.

 

My post was an attempted pitch at the basic inferred HDL to match figure 4 and not drilling down through the various other areas you must consider when targeting the FPGA fabric to fully meet your requirements. (unless you only need low resolution in which case routing delays to internal registers may be down in the noise)

 

For me metastability protection is all about ensuring that any asynchronous signal that feeds more than one piece of logic has gone through a double register stage to reduce the probability of becoming metastable. (more regs reduces it further) The fundamental issue here is when a signal goes metastable (i.e. sits at an undefined logic level for that clock cycle) you will find one piece of logic may see the signal as a '1' while another a '0'. This is what causes unknown behaviour such as a state machine entering an unknown state.

 

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Anonymous
Not applicable
12,313 Views

Thank you, Andrew. I didn't mean to ignore your comment! That's where my metastability question came from. I understand how to implement that Figure 4 in VHDL, I just originally chose not to because I wasn't sure what those other columns of flip-flops were for. Thanks!

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Voyager
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Registered: ‎04-21-2014

andrewlan wrote:

 

My post was an attempted pitch at the basic inferred HDL to match figure 4 .

 


Exactly.  It's not that difficult either.  No need to clutter things up, eh?

 


andrewlan wrote:

The code you have written does not describe fig 4 in your spec.

 

You need to think like this...

 

process(clk)
begin
 [text removed for formating]

 

 

etc..

 


Pretty good, and clearly what the original poster needed help on.  

 

If I may expand your on topic post:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity figure4 is
  generic(
    G_NUM_STAGE_FLIP_FLOPS : integer range 2 to 8 := 4
  );
  port(
    iCLK000       : IN  std_logic;
    iCLK090       : IN  std_logic;
    iCLK180       : IN  std_logic;
    iCLK270       : IN  std_logic;
    iStart_Async  : IN  std_logic;
    oSync000      : OUT std_logic;
    oSync090      : OUT std_logic;
    oSync180      : OUT std_logic;
    oSync270      : OUT std_logic
  );
end entity figure4;

architecture rtl of figure4 is
  signal clks : std_logic_vector(3 downto 0);
 
  type  tSampleArray is array (3 downto 0) of std_logic_vector(G_NUM_STAGE_FLIP_FLOPS-1 downto 0);
  signal sample_clk_stage : tSampleArray := (others => (others => '0'));
 
  attribute ASYNC_REG : string;
  attribute ASYNC_REG of sample_clk_stage : signal is "TRUE"; 
  -- NOTE:  ASYNC_REG has many side effects, including RLOC'ing registers
  --        into same slice, preventing SRL inference, etc.  See UG901 and
  --        UG912 for more information.
begin

 

  clks <= (0 => iClk000, 1 => iClk090, 2 => iClk180, 3 => iClk270);

 

  CLK_0_270_GENERATE : for i in 0 to 3 generate
    process(clks(i))
      begin
        if rising_edge(clks(i)) then
          sample_clk_stage(i) <= sample_clk_stage(i)(sample_clk_stage(i)'high - 1 downto 0) & iStart_Async;
        end if;
    end process;
  end generate CLK_0_270_GENERATE;
 
  oSync000 <= sample_clk_stage(0)(sample_clk_stage(0)'high);
  oSync090 <= sample_clk_stage(1)(sample_clk_stage(1)'high);
  oSync180 <= sample_clk_stage(2)(sample_clk_stage(2)'high);
  oSync270 <= sample_clk_stage(3)(sample_clk_stage(3)'high);

 

end architecture rtl;

 

If you use the above, peta32387, you may continue to use BUFG's.  There are other issues you'll have to deal with in your FPGA, but in the absense of a professor who knows FPGA design and the time to mentor you, you'll have to cross those bridges when you reach them.  Don't get discouraged, though. 

 

 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Explorer
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Registered: ‎06-25-2014

Very nice Morgan! :)

 

You now owe Morgan a beer for writing an elegant piece of vhdl that will get top marks and uses many elements of the vhdl language!

 

 

 

 

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