UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor adrialex
Visitor
4,011 Views
Registered: ‎08-05-2009

Multiplier Code problem

I have this code below and i can't determine whether or not i did the right thing on my portmaps. All i get is a "00000000" output for my res. The components that I used are functioning right. Pls help me fix my code. Thank You.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multiplier is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           en : in  STD_LOGIC;
           opA : in  STD_LOGIC_VECTOR (3 downto 0);
           opB : in  STD_LOGIC_VECTOR (3 downto 0);
           res : out  STD_LOGIC_VECTOR (7 downto 0);
           done : out  STD_LOGIC);
end multiplier;

architecture Behavioral of multiplier is
signal number : STD_LOGIC_VECTOR (3 downto 0) := "0001";
signal tempA : STD_LOGIC_VECTOR (3 downto 0);
signal tempB : STD_LOGIC_VECTOR (3 downto 0);
signal tempC : STD_LOGIC_VECTOR (3 downto 0);
signal tempD : STD_LOGIC_VECTOR (3 downto 0);
signal tempE : STD_LOGIC;

COMPONENT clahead_addr
    PORT(
        clk : IN std_logic;
        operandA : IN std_logic_vector(3 downto 0);
        operandB : IN std_logic_vector(3 downto 0);
        carry_in : IN std_logic;         
        sum : OUT std_logic_vector(3 downto 0);
        carry_out : OUT std_logic
        );
    END COMPONENT;
   
    COMPONENT shifter
    PORT(
        clk : IN std_logic;
        rst : IN std_logic;
        op1 : IN std_logic_vector(3 downto 0);
        op2 : IN std_logic_vector(3 downto 0);
        din : IN std_logic;         
        out1 : OUT std_logic_vector(3 downto 0);
        out2 : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   
    --Inputs
    SIGNAL operand1 :  std_logic_vector(3 downto 0);
    SIGNAL operand2 :  std_logic_vector(3 downto 0);
    SIGNAL done1 : std_logic;
   

    --Outputs
    SIGNAL sum :  std_logic_vector(3 downto 0);
    SIGNAL carry_out1 :  std_logic;
    SIGNAL carry_out2 :  std_logic;
    SIGNAL outA :  std_logic_vector(3 downto 0);
   SIGNAL outB :  std_logic_vector(3 downto 0);
   
begin

    uut1: clahead_addr PORT MAP(
        clk => clk,
        operandA => operand1,
        operandB => operand2,
        carry_in => '0',
        sum => sum,
        carry_out => carry_out1
    );
   
    uut2: shifter PORT MAP(
        clk => clk,
        rst => rst,
        op1 => sum,
        op2 => tempB,
        out1 => outA,
        out2 => outB,
        din => carry_out1
    );
process (rst, en, clk, tempB, number, tempA, outA, outB)
begin
    if rst = '1' then
        res <= "00000000";
        operand1 <= "0000";
        operand2 <= "0000";
        tempA <= "0000";
        tempB <= "0000";
        tempC <= "0000";
        tempD <= "0000";
        tempE <= '0';
    elsif en = '1' then
        tempA <= opA;
        tempB <= opB;
    elsif clk'event and clk = '1' then
        if tempB(0) = '1' and number = "0001" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "0010";
        elsif tempB(0) = '1' and number = "0010" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "0100";
        elsif tempB(0) = '1' and number = "0100" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "1000";
        elsif tempB(0) = '1' and number = "1000" then
            operand2 <= tempA;
            operand1 <= outA;
            tempB <= outB;
            number <= "0000";
           
        elsif tempB(0) = '0' and number = "0001" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "0010";
        elsif tempB(0) = '0' and number = "0010" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "0100";
        elsif tempB(0) = '0' and number = "0100" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "1000";
        elsif tempB(0) = '0' and number = "1000" then
            operand2 <= "0000";
            operand1 <= outA;
            tempB <= outB;
            number <= "0000";
           
        elsif number = "0000" then
            res(7) <= operand1(3); res(6) <= operand1(2); res(5) <= operand1(1); res(4) <= operand1(0);
            res(3) <= tempB(3); res(2) <= tempB(2); res(1) <= tempB(1); res(0) <= tempB(0);
            number <= "0001";
        end if;
       
    end if;   
   
end process;

end Behavioral;

Message Edited by adrialex on 08-09-2009 12:38 AM
0 Kudos
3 Replies
Advisor eilert
Advisor
3,985 Views
Registered: ‎08-14-2007

Re: Multiplier Code problem

Hi adrialex,

 

In your multiplier process you are using some strange asynchronous enable:

 

     elsif en = '1' then
        tempA <= opA;
        tempB <= opB;

 

As long as you keep this "Enable" active your circuit won't do anything, because the synchronous part never starts. At least not in simulation.

Loading data with an asynchrounous preset  looks very dangerous do me. Maybe you schould consider to move it into the synchronous part of your process.

Is the en signal used correctly in your testbench?

 

 

Besides:    

res(7) <= operand1(3); res(6) <= operand1(2); res(5) <= operand1(1); res(4) <= operand1(0);
res(3) <= tempB(3); res(2) <= tempB(2); res(1) <= tempB(1); res(0) <= tempB(0);

 

is more code than neccessary:

res(7 downto 4) <= operand1;

res(3 downto 0) <= tempB;

 

will do it, and

 

res <=  operand1 & tempB;

 

is even shorter.

But this has nothing to do with the functionality of your code.

 

Have a nice synthesis

  Eilert

0 Kudos
Visitor adrialex
Visitor
3,977 Views
Registered: ‎08-05-2009

Re: Multiplier Code problem

I have proper signal handling using my en in my test bench. I can't figure out why my output is always 0. My rst goes back to 0 after one clock cycle and my en goes to 1 after my rst becomes 0 and goes back to 0 after one clock cycle. Pls help me. Thank You
0 Kudos
Historian
Historian
3,962 Views
Registered: ‎02-25-2008

Re: Multiplier Code problem


adrialex wrote:
I have proper signal handling using my en in my test bench. I can't figure out why my output is always 0. My rst goes back to 0 after one clock cycle and my en goes to 1 after my rst becomes 0 and goes back to 0 after one clock cycle. Pls help me. Thank You
 

Of course your code will simulate correctly, as the construct in your process is legal VHDL.

 

However, your code infers both an asynchronous reset (if rst = '1' then ....) as a well as an asynchronous load (elsif en = '1' then ...). The FPGA architecture does not support an asynchronous load, and if you go back and look at your synthesis report, you should see some complaints about this, if not outright error messages.

 

ALSO:

 

In a synchronous process, the ONLY signals that should be on the sensitivity list are the clock and the asynchronous reset. Nothing else.

 

Anyways, it is obvious why your res output remains zero all the time -- I assume that your test bench asserts the asynchronous reset, which clears res, operand1 and operand2 as well as the tempX signals. Note that your code does NOT explicitly reset the signal number (which isn't declared, either) so its value in simulation will be "U", so none of the if/elsif statements will match and therefore no new assignments to anything occur. When you DO assert en, the only things that happens are the two assignments to tempA and tempB. Of course there is no declaration of the signals opA and opB, so one assumes another compiler complaint will be issued.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos