08-24-2015 12:56 PM
i have a constraint in my ucf file - NET "datain" LOC = AL37;
i use synplify to synthesize my design. i do a constraint check and the above constraint is fine.
after synthesis, i take the edf file and put it in xilinx ise 14.1 for implementation/bitgen. i use the same ucf (which i used for synplify synthesis).
the entire process completes without errors, the bitfile also works fine. but in the ngdbuild warnings, i get this -
ConstraintSystem - A target design object for the Locate constraint '<NET "datain_c" LOC = AL37>' could not be found and so the Locate constraint will be removed.
but in my pinout report, the datain pin is still defined at AL37 (so i guess the location constraint was still met).
I wanted to know if this warning is important or if it can be ignored (because the pinout report still shows proper placement)
If I do want to get rid of this warning, what do i need to do?
thanks in advance ...
08-24-2015 03:30 PM
> NET "datain" LOC = AL37;
is not the same as:
> NET "datain_c" LOC = AL37
08-24-2015 03:35 PM
yes .. i know ... datain is not the same as datain_c ... so my question is why is this coming up as a ndg warning when i specify datain on loc AL37 ... ?
thanks and regards,
08-24-2015 03:37 PM
> my question is why is this coming up as a ndg warning
Search your design files for datain_c it is probably there somewhere.
08-24-2015 04:37 PM
ive checked the ucf. i dont have a datain_c ... in the ucf file i just have datain defined in the design either. could it be that synplify is renaming the signal somehow?
08-24-2015 11:57 PM
Yes that might be possible if this UCF file is being generated by Synplify tool.
08-25-2015 12:35 AM
the ucf i am using is a xilinx ucf only. lets call this design.ucf
i use design.ucf and convert it to sdc in synplify.
i synthesize the design using the design.sdc which generates the .edf file
then i take the .edf into xilinx ise and implement the design using design.ucf as the constraint file.
so is there some other constraint file that i should be using from synplify?
if so, why is my pinout report still OK after i implement the design (using design.ucf) in xilinx?