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Newbie
Newbie
7,095 Views
Registered: ‎08-08-2015

Need Urgent Help : Using VIVADO Design Suite for PCI Express 3.0, 8 lane, and AXI Interfaces for Video Processing

My scenario is as follows :-

 

1) I am building a Image Processing Application and using VIVADO HLS for that.

2) I have synthesized my design using VIVADO HLS, and export it as IP-XACT format.

3) I have imported it in VIVADO Design Suite, and added to the IP catalog, in a new project created.

4) Since I am building an image processing pipeline, I am using AXI Stream interfaces, 1 input stream, and 1 output stream, and mentioned that in the HLS tool itself..

5) I have a Virtex 7 690T FPGA, and have accordingly chosen the board throughout the HLS process, and the project.

6) We want to use a PCI Express 3.0, through DMA access to the CPU.

7) Now I am stuck here regarding how to proceed forward, I have gone through most of the Xilinx documentation, but am still not clear about what to do from here on.

8) There are these 3 variables for me, AXI Stream Interface, DMA, PCI Express 3.0, all I have right now is the IP of the Image Processing pipeline that I generated through VIVADO HLS.

9) Also at a later stage we would like to stream in Video, and process it through our image processing pipeline.

 

Please help me with an overview of steps that I need to follow to get my design together and working on a real FPGA hardware with my Computer(windows OS), as in what Xilinx IP blocks do I need to use, how will I be able to exploit the maximum bandwidth from the PCI Express Interface in my specific case of send image through a stream, what tools will I need to use at every stage.

 

I would be highly grateful if you guys can help me, we have a dealine to meet.

Please let me know if we need any extra information.

 

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Voyager
Voyager
7,040 Views
Registered: ‎04-21-2014

School project?

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