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Anonymous
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Need clever solution for ugly async Third-Party IP problem

Hi All. Before endeavoring on this nasty quest I thought it would be nice to see what some of you could suggest. I have a situation on a Xilinx 4- 200 device where the IP core supplied by a thrid party has an async bug or a miscontrained portion of the design. Unfortuneatly the IP core consists of the top level design that calls the "user developed" portion. The IP is supplied as an ngc file (5% of chip overhead) with all the constraints embedded, and the design consists of several fast and tricky clock domains. In any case I have been able to get the design to work on the prototype especially when the user logic is less then half of the chip (even got some to work at 80% !!) but requires creating multiple iterations of place and routes and bit files. What I would like to do is find a way to extract the IP placement and routing from an existing working iteration of the design and use this to create the new IP for the user logic. I have no way of contacting the IP developer nor have phsyical access to the system. Suggestion are welcomed, thank you.
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Historian
Historian
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Registered: ‎02-25-2008


alo_xilinx wrote:
Hi All. Before endeavoring on this nasty quest I thought it would be nice to see what some of you could suggest. I have a situation on a Xilinx 4- 200 device where the IP core supplied by a thrid party has an async bug or a miscontrained portion of the design. Unfortuneatly the IP core consists of the top level design that calls the "user developed" portion. The IP is supplied as an ngc file (5% of chip overhead) with all the constraints embedded, and the design consists of several fast and tricky clock domains. In any case I have been able to get the design to work on the prototype especially when the user logic is less then half of the chip (even got some to work at 80% !!) but requires creating multiple iterations of place and routes and bit files. What I would like to do is find a way to extract the IP placement and routing from an existing working iteration of the design and use this to create the new IP for the user logic. I have no way of contacting the IP developer nor have phsyical access to the system. Suggestion are welcomed, thank you.

Dump the core.

----------------------------Yes, I do this for a living.
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Registered: ‎07-15-2008

My suggestion too is dump the core… re-design the section yourself.

   

Just as an aside, I’ve seen a few FPGA projects being posted on “rent a coder” and people are offering to undertake work for almost no money.

Then questions start turning up on this forum from various “fpga newbys” that are so specific they are defiantly people who have taken this work.

   

Be warned anyone who is buying IP from that site!

 

 

   Bobster
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Contributor
Contributor
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Registered: ‎06-22-2009

Hi,

 

Here is the deal - .ngc files are effectively netlists so all of the constraints are built in.

 

They are used by IP vendors so that they can deliver the function without releasing their source code and thus protecting their investment in generating it. This is because it is very difficult to reverse engineer anything useful from the netlist. Their business model relies on selling the IP many times. It is in their interest to make sure that it works and is easy to use. This is indeed my experience of a well known UK IP vendor.

 

If you cannot contact the developer or obtain the source code then you should not be using the core. Which is pretty much the same advice as the previous replies.

 

Best wishes

PM

Message Edited by flitch@mbda on 08-21-2009 03:17 AM
Message Edited by flitch@mbda on 08-21-2009 06:53 AM
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