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2,256 Views
Registered: ‎12-22-2009

Need help on this design issue

Hi,

 

In my design, output of 14 bit ADC is 204.8 MSPS complex data consisting of alternate samples of I and Q. I need to separate I and Q into two streams of samples at 102.4 MSPS. I have used a PISO shift register at the ADC output to get a serial stream at 204.8 MSPS.Then I have used a 1: 2 demultiplexer(by clocking at 102.4MHz) to segregate alternate samples of I and Q.The I and Q stream is then sent to FFT processor.My question is: is there a better way to implement the separation of I and Q samples from the complex number stream(without using P2S conversion and 1:2 demux combination)?Many thanks in advance for any help.

 

Jaideep

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woutersj
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Registered: ‎07-27-2009

I would guess that the P2S operation is not needed. Use a 28bit register at the fast clock that contains I and Q. After 2 cycles, you retime the I and Q into the half speed clock domain. Done.

 

A DCM can be very convenient to generate the divided clock.

 

Cheers,

Johan

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