UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer oft
Observer
2,796 Views
Registered: ‎07-03-2017

Negative edge FFs

Jump to solution
This isn't as much of a question, as something I've never come across, but is a feature in Xilinx FPGAs.
I haven't seen them in use yet, and I was wondering: why would they he used, where, is it a bad practice to use them, and I'd like to see an example

Thank you,
Oft
Tags (3)
0 Kudos
1 Solution

Accepted Solutions
Historian
Historian
4,650 Views
Registered: ‎01-23-2009

Re: Negative edge FFs

Jump to solution

Negative edge fabric flip-flops are rarely used...

 

While it is true that there is nothing "magic" about the rising edge of the clock - it is perfectly acceptable to do your entire design using only negative edge flip-flops (instead of positive edge flip-flops) - the design, tools and FPGA architecture would all be perfectly happy with it. Of course, why would you? - the entire community agrees that we all use rising edge flip-flops (so don't do this...),

 

So the next question is "are there applications where you use a mixture of positive and negative edge flip-flops". The answer is yes, but generally only in very limited applications.

 

For "generic" logic, using both edges is a bad idea. VERY early design styles (two phase non-overlapping clock latch based design used in the 1970s) did this - half the logic was implemented between the rising and falling edge latch and the other half between the falling and rising. However, now that we all use flip-flops no one does this anymore - it is inefficient for a whole bunch of reasons (increased power, sensitivity to duty cycle distortion, more difficulty in pipelining, Amdahl's law, ....)

 

So when would we use it. Many I/O interfaces use Double Data Rate transmission. As a result, we need DDR flops, which really are FFs clocked on both edges. To feed the negative edge input of an ODDR (D2), though, you must somewhere cross between a positive edge FF and the negative edge FF to ultimately feed the negative edge FF in the ODDR. You can do this in the last timing path (a positive edge fabric FF driving the D2 input of the ODDR), but this 1/2 clock cycle path is actually easier to do entirely in the fabric (rising edge fabric FF -> falling edge fabric FF -> D2 of ODDR).

 

There are other examples involving odd clocks. For example, lets say you have two clocks from the same MMCM where one output is 1ns later than the other (clkb is 1ns later than clka). Crossing from clka^ to clkb^ is a 1ns path, which is very hard (or impossible) to do. However clka^ -> clb v -> clkb^ has a 6ns path and a 5ns path (assuming clka and clkb are both 100MHz clocks), both of these paths are easy to do.

 

There can be more esoteric applications (one can envision a 1.5 clock cycle mutlicycle path), but I have never come across a need to do something like this.

 

So, there are applications, but they are rare...

 

Avrum

Tags (1)
2 Replies
Historian
Historian
4,651 Views
Registered: ‎01-23-2009

Re: Negative edge FFs

Jump to solution

Negative edge fabric flip-flops are rarely used...

 

While it is true that there is nothing "magic" about the rising edge of the clock - it is perfectly acceptable to do your entire design using only negative edge flip-flops (instead of positive edge flip-flops) - the design, tools and FPGA architecture would all be perfectly happy with it. Of course, why would you? - the entire community agrees that we all use rising edge flip-flops (so don't do this...),

 

So the next question is "are there applications where you use a mixture of positive and negative edge flip-flops". The answer is yes, but generally only in very limited applications.

 

For "generic" logic, using both edges is a bad idea. VERY early design styles (two phase non-overlapping clock latch based design used in the 1970s) did this - half the logic was implemented between the rising and falling edge latch and the other half between the falling and rising. However, now that we all use flip-flops no one does this anymore - it is inefficient for a whole bunch of reasons (increased power, sensitivity to duty cycle distortion, more difficulty in pipelining, Amdahl's law, ....)

 

So when would we use it. Many I/O interfaces use Double Data Rate transmission. As a result, we need DDR flops, which really are FFs clocked on both edges. To feed the negative edge input of an ODDR (D2), though, you must somewhere cross between a positive edge FF and the negative edge FF to ultimately feed the negative edge FF in the ODDR. You can do this in the last timing path (a positive edge fabric FF driving the D2 input of the ODDR), but this 1/2 clock cycle path is actually easier to do entirely in the fabric (rising edge fabric FF -> falling edge fabric FF -> D2 of ODDR).

 

There are other examples involving odd clocks. For example, lets say you have two clocks from the same MMCM where one output is 1ns later than the other (clkb is 1ns later than clka). Crossing from clka^ to clkb^ is a 1ns path, which is very hard (or impossible) to do. However clka^ -> clb v -> clkb^ has a 6ns path and a 5ns path (assuming clka and clkb are both 100MHz clocks), both of these paths are easy to do.

 

There can be more esoteric applications (one can envision a 1.5 clock cycle mutlicycle path), but I have never come across a need to do something like this.

 

So, there are applications, but they are rare...

 

Avrum

Tags (1)
Observer oft
Observer
2,701 Views
Registered: ‎07-03-2017

Re: Negative edge FFs

Jump to solution
Thank you! That was very informative!
0 Kudos