03-27-2013 08:59 PM
I am just getting into the realm of FPGA design and have done much reading in the recent weeks. I am fairly confident I can answer my own question but I just wanted to confirm.
1. I have an incoming 24MHz clock
2. I translate this to an internal signal via an IBUFG
3. I immediately use a DCM to phase synchronize and PLL this 24MHz up to 300MHz signal
4. I BUFG this 300MHz signal to fan out to my logic
My question is:
In my .UCF timing constraints for clocking, I have ONLY specified the constraint on the 300MHz signal and am assuming that it will ripple up stream through the DCM/PLL and to the pin. Could somebody please confirm that my attempt at simplifying the timing description is valid (as my interpretation of the timing constraints documentation is that yes it is valid to do this on just the one CLK).
03-27-2013 10:53 PM
No, you have it the wrong way around. In your UCF you should only need to constrain the INPUT clock, 24MHz. The tools are smart enough to ripple the constraint through the clock management and into the logic, not from the logic back to the pin.
Incidentally, depending on how your 24MHz clock is routed (i.e. does it go to other logic as well as the DCM?), you may need to add a BUFG after the IBUFG (yes, confusing names). If it ONLY routes from the IBUFG to the DCM, you probably won't need it.
03-28-2013 07:59 AM
Generally, if one applies a period constraint to the input clock (24 MHz in your case) it is propagated through the connected DCM to all outputs (as a new period constraint for all those clocks).
What part are you using, and what version of software?
What is the reported jitter from the tools (what is being taken away from the time period because of input clock jitter, system jitter, and synthesis jitter -- converting the 24 MHz to 300 MHz)? I presume you have M=25, and D=2 for your M and D values (to get 300 from 24).
04-07-2013 11:30 PM
04-08-2013 01:06 AM
I have seen occasional tools and performance issues when the multiplication and divide constants for frequency conversion are considerably different. I am not sure why this is but it could be something to look out for.
04-08-2013 07:26 AM
The 3E has no PLL. It has DCM's. Entirely different implementation.
Jitter in, and jitter out, is very important.
Jitter in will cause it to lose lock. For high values of M/D, the CLKFX output may have substantial jitter.
For example, driving a second DCM from a first DCM with both in frequency sythesis mode (CLKFX->CLKIN, CLKFX out), is not supported for the very reason that the jitter out on CLKFX is too great for hte next DCM.
Two DCM's in tandem generally never makes any sense (don't do it).
04-08-2013 06:44 PM
good to know the words of caution. I'll review the input jitter specs and I'm assuming I can find a constraint that will allow me to add them onto this input CLK so that it will ripple through to my 300MHz logic's timing analysis.
One last timing question. I have decided to use my CLK2X that I am using as my CLKFB signal. Could you just confirm that the timing analysis will also identify this relationship from CLKIN to CLK2X in timing analyses if a constraint is defined only for my CLKIN signal.
04-09-2013 07:14 AM
Yes, the constraint on the input should be passed through (and modified for the new output period).