02-09-2016 11:59 PM
the manufacturers of Zynq 7020 SoC which I am going to buy do not have PCI express x1 neither USB 3.0 support. Can I implement these funcionalities in PL and output the data through GPIO or any other pins? If this is achievable ? Is there any info on that? I have no budget to buy IP cores, so I will be doing all the coding myself, but I need to know if this is technically possible with this hardware. And if it is, how many logic cells would this take for both protocols (aprox) ?
Thank you very much in advance.
02-11-2016 11:02 AM
USB3.0 and PCIe is defined as a serial interface that requires Gigabit Transceivers (GTs). Unfortunately, the 7020 device you mentioned does not have these GT primitives; in the Zynq-7000 family, only these devices implement GTs:
In addition to the device requiring GTs, you cannot utilize the hardened USB controllers that Zynq provides, as there is not a mechanism to route the ULPI signals to the PL and then using a shim IP to convert it to the GT protocol.
If you wish to implement these IPs, please consider using the devices I listed above.
02-28-2016 10:46 PM