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nulik
Visitor
Visitor
14,281 Views
Registered: ‎02-06-2016

PCI Express x1 & USB 3.0 in Zynq 7020

Hi,

the manufacturers of Zynq 7020 SoC which I am going to buy do not have PCI express x1 neither USB 3.0 support. Can I implement these funcionalities in PL and output the data through GPIO or any other pins? If this is achievable ? Is there any info on that? I have no budget to buy IP cores, so I will be doing all the coding myself, but I need to know if this is technically possible with this hardware. And if it is, how many logic cells would this take for both protocols (aprox) ?

 

Thank you very much in advance.

Nulik

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robn
Moderator
Moderator
14,179 Views
Registered: ‎11-10-2010

Nulik,

 

USB3.0 and PCIe is defined as a serial interface that requires Gigabit Transceivers (GTs). Unfortunately, the 7020 device you mentioned does not have these GT primitives; in the Zynq-7000 family, only these devices implement GTs:

7015

7030

7035

7045

7100

 

In addition to the device requiring GTs, you cannot utilize the hardened USB controllers that Zynq provides, as there is not a mechanism to route the ULPI signals to the PL and then using a shim IP to convert it to the GT protocol. 

 

If you wish to implement these IPs, please consider using the devices I listed above.

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muzaffer
Teacher
Teacher
13,414 Views
Registered: ‎03-31-2012

To implement PCIe or USB3, you need a transceiver. As you say, 7020 doesn't have either transceiver so you need this chip externally. Consider this part: http://www.nxp.com/products/interface-and-connectivity/interface-and-system-management/pci-express/pcie-physical-layer-phy-devices/pci-express-stand-alone-x1-phy:PX1011B

To talk to it, you just need digital IO which is available in PL.
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