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Visitor macintyre
Visitor
9,902 Views
Registered: ‎02-25-2015

POR and INIT B

wrt XC7A35T-1FT256.

Hearing from an SME here at work that  putting a POR circuit on INIT_B will be fine for initial configuration. If the POR circuit pulls INIT_B after initial configuration the FPGA configuration is not reset. Is this correct?

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6 Replies
Professor
Professor
9,892 Views
Registered: ‎08-14-2007

Re: POR and INIT B

It sounds right.  INIT_B will hold off the start of configuration, but it does not reset the configuration.  PROGRAM_B does that.  With the 7-seres, PROGRAM_B went from a level-triggered reset to an edge-triggered reset.  So in fact INIT_B is the only way to hold off configuration in master modes.  Holding PROGRAM_B low will no longer hold off configuration.  It may not be necessary to hold INIT_B low under most conditions, since there is a reasonably long internal reset period after the supplies reach the internal POR threshold before configuration starts.   Slow rise time on the Vcco used by the configuration flash is usually the reason to hold off configuration on power-up.

-- Gabor
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Visitor macintyre
Visitor
9,889 Views
Registered: ‎02-25-2015

Re: POR and INIT B

Is there a document that explains the internal POR of the 7 series.

 

Specifically I have a POR circuit on INIT_B_0. PROGRAM_B is pulled high. The datasheet indicates that after initial config if INIT_B is pulled low the FPGA will not reconfigure. My sequencing is set up such that 1 (Vccint) enables 1.8 (Vccaux) enables  3.3 (Vcco).

It seems to make sense that if 1 or 1.8 is lost the FPGA will reconfigure. What happens, if anything, to the internal POR if 3.3 (Vcco) is lost.

Hence the request for the internal POR explanation.

 

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Professor
Professor
9,883 Views
Registered: ‎08-14-2007

Re: POR and INIT B

I don't see any list of thresholds, if its ramp time that worries you.  However since it is possible to use a lower Vcco_0 and Vcco_14 than 3.3V, it surely has a lower threshold.  On the other hand the internal power-on reset time is listed in ds181 as from 10 to 50 ms, which gives a long time for your Vcco to ramp up to 3.3V after any reasonable internal threshold is met.  Note that you also need to check the SPI flash data sheet to see if it has a minimum start-up delay time, which could also be in the milliseconds.

-- Gabor
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Xilinx Employee
Xilinx Employee
9,872 Views
Registered: ‎10-11-2007

Re: POR and INIT B

Vccint, Vccbram, Vccaux and Vcco_0 are required to be up for the part to come out of POR and continue with the INIT cycle (in simple terms). After that Vcco_0 is no longer monitored. So any Vcco can go down from a POR perspective without loosing configuration or causing a POR event. Only the first three mentioned above will do that. Pulling INIT_B before INIT completes will delay configuration, but obviously not after that.

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Xilinx Employee
Xilinx Employee
9,861 Views
Registered: ‎08-01-2012

Re: POR and INIT B

macintyre initial post says-----Hearing from an SME here at work that  putting a POR circuit on INIT_B will be fine for initial configuration.

 

 

Please note that internal Power on reset (POR) exists in FPGA. It monitors basically VCCINT, VCCAUX and VCCO -Configuration bank supply rails. 

 

If you wish to provide POR circuit externally also, then POR on Program_B is standard practice .  

 

The POR timing information can be found in page-82 of http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 

 

FYI: Please note that "Pulsing the PROGRAM_B signal or power-on reset is required to reset the configuration interface." This was mentioned in page 96 of UG470.

 

 

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Professor
Professor
9,847 Views
Registered: ‎08-14-2007

Re: POR and INIT B


@umamahe wrote:

@macintyre initial post says-----Hearing from an SME here at work that  putting a POR circuit on INIT_B will be fine for initial configuration.

 

 

Please note that internal Power on reset (POR) exists in FPGA. It monitors basically VCCINT, VCCAUX and VCCO -Configuration bank supply rails. 

 

If you wish to provide POR circuit externally also, then POR on Program_B is standard practice .  

 

The POR timing information can be found in page-82 of http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 

 

FYI: Please note that "Pulsing the PROGRAM_B signal or power-on reset is required to reset the configuration interface." This was mentioned in page 96 of UG470.

 

 


That's true if you want for example a brown-out reset to reconfigure the FPGA.  However holding PROGRAM_B low at start-up is not necessary because of the internal POR, and in the 7 series (this is new) it will not delay the start of configuration.  That's the reason to apply the board-level POR signal, presumably with a milliseconds-long guaranteed width, to the INIT_B signal.

 

Also you say the VCCO is monitored for internal POR, but even if the chip has a variable level to detect a valid voltage on Vcco based on the CFGBVS pin, it still needs to release before the lowest valid 2.5V Vcco level.  For a 3.3V-powered configuration with a slow rise time, this may come too soon to reliably hold off configuration until the attached flash is operational.

-- Gabor
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