Pin Placement of I2C / System Management Bus Clocks and Data lines

[polyee13]

Do I2C/ SMBUS clock signals have to be routed to a GCLK pin of a Spartan-6 device? I'm running into some layout issues and a suggestion was made to move these clock and data signals from their current bank to another bank, which doesn't have any global clock pins. 

[rcingham]

If the I2C/SMbus slave block you are using treats the SCK pin as a clock (rather than oversampling it for rising and falling edges), then it is doing things the hard way!

[polyee13]

Not sure if I understand your reply. Let's assume that it treats the clock lines as a clock.

[bassman59]

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@polyee13 wrote:

Not sure if I understand your reply. Let's assume that it treats the clock lines as a clock.

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You missed his point. You should use your FPGA's high-speed global clock to oversample the I2C signals and look for levels. Remember that I2C isn't edge sensitive. 

[rcingham]

"Not sure if I understand your reply. Let's assume that it treats the clock lines as a clock."

Don't assume. Find out.
If you looked at the HDL for the I2C block, would you understand it?

[polyee13]

So with that said, it really shouldn't matter if the I2C clock lines are allocated to a Global clock pin. It's not like the I2C clock is a clock that will be distributed through the FPGA for the logic other than the I2C core.

[gszakacs · Accepted solution]

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@polyee13 wrote:

So with that said, it really shouldn't matter if the I2C clock lines are allocated to a Global clock pin. It's not like the I2C clock is a clock that will be distributed through the FPGA for the logic other than the I2C core.

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Correct.

To add to that, you should know that unless you have an FPGA or CPLD with hysteresis on the

inputs (Schmitt triggers) you should not even consider using the SCL line as a clock.  Its rise

time is much too slow.

-- Gabor

[bassman59]

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@polyee13 wrote:

So with that said, it really shouldn't matter if the I2C clock lines are allocated to a Global clock pin. It's not like the I2C clock is a clock that will be distributed through the FPGA for the logic other than the I2C core.

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The I2C clock isn't used as a clock, full stop. It's a flag that, when high, indicates that the state of SDA is a valid logic level. When SCK is low, SDA can change, but SDA must be stable some setup time before the rise of SCK and cannot change until after SCK falls. So what is usually done is for the FPGA to oversample SCK, note when its rising edge occurs, and then wait a few (fast system) clock ticks before actually reading the value on SDA. You want to wait because, as noted, the rise time on SCK and SDA are not all that fast due to resistive pull-ups.