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Visitor
Visitor
6,428 Views
Registered: ‎01-21-2014

Please reply me soon..

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I have generated a BPSK signal and PPS(pulse per second) signal in virtex 6 FPGA and generated a bit file and tested the BPSK signal in the hardware.It's working fine.

By taking a copy of those files with port signals reorder and PPS(pulse per second) signal generation logic is changed.I generated bit file with this and tested the BPSK signal in hardware.But it is not giving the same results as before.I have created the same scenario for both cases.

Can you please let me know why this problem occur??

 

Thanks a lot...

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Professor
Professor
10,598 Views
Registered: ‎08-14-2007

Re: Please reply me soon..

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Another common issue is timing.  If your design is not properly constrained, then any change can affect timing in a way that causes it to fail.

-- Gabor

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Xilinx Employee
Xilinx Employee
6,389 Views
Registered: ‎07-21-2014

Re: Please reply me soon..

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hi,

 

as you said, you have reordered the ports. Have you changed the UCF file accordingly?

 

thanks,

Shreyas

 

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Professor
Professor
10,599 Views
Registered: ‎08-14-2007

Re: Please reply me soon..

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Another common issue is timing.  If your design is not properly constrained, then any change can affect timing in a way that causes it to fail.

-- Gabor

View solution in original post

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Moderator
Moderator
6,371 Views
Registered: ‎07-21-2014

Re: Please reply me soon..

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Hi,

 

Can you elaborate your query with the actual changes you have done.

List out some scenario for better understanding.

 

Thanks,
Anusheel
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Visitor
Visitor
6,353 Views
Registered: ‎01-21-2014

Re: Please reply me soon..

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Thank you friend..

It's working fine..There was problem in the hardware...

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Moderator
Moderator
6,339 Views
Registered: ‎07-21-2014

Re: Please reply me soon..

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Hi,

 

Please close the thread by marking the relevant answer as accepted solution.

 

Thanks,
Anusheel
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