10-21-2013 10:07 AM
Currently I am porting all my IP cores from ISE to Vivado. The ISE IP cores are described by the MPD/PAO files.
In some of my IP cores I use cores generated by the IP core generator (like FIFOs and dividers). My problem is now how to package an IP core with Vivado including the XCI files from the core generator.
My preferred solution would be to not use the CoreGenerator at all (as it is really inflexible). Instead I would like to use the "basic_fifo_fg.vhd" modules inside the "proc_common" library. For the divider I would like to instanciate directly from the "div_generator" library. This works fine for packaging and implementing an IP cores. But getting the simulation to work was not possible due to missing libraries. Adding manually the files of "proc_common" to a library did also not help.
That's why I am thinking about using the "old" way and just stick to the output of CoreGenerator and include this cores to the IP core package. But I have not yet found a way to do so. The documentation seems not to cover this case.
I would be thankful for any hint on this issue.
10-21-2013 03:53 PM
Check this thread,
and this one:
It's all RTL under the hood (most of it unencrypted). And a quite a bit of the Xilinx code is good code, especially the new AXI stuff. Xilinx just seems to like putting up roadblocks to actually using those modules. (Other than the "look at the nifty wizards we have." Sigh...)
10-22-2013 02:46 AM
You can refer to page 159 of the following document:
There is a lab that demonstrates how to convert legacy EDK IPs to use with Vivado IPI.