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Explorer
Explorer
17,478 Views
Registered: ‎09-22-2010

Portmapping bidirectional ports

hi,

when it comes to connecting two bidirectional ports in Vhdl what can be done? does there exist some simple way such as 

defining a bidirectional signal?

 

 

thanks guys,

    regards,

     bouvett

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17 Replies
Xilinx Employee
Xilinx Employee
17,476 Views
Registered: ‎01-03-2008

Re: Portmapping bidirectional ports

You don't need anything more than a standard signal declaration to connect two bi-directional ports.

 

Hopefully, you are doing this in a test bench and not attempting to do this within a single FPGA design.

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Explorer
Explorer
17,474 Views
Registered: ‎09-22-2010

Re: Portmapping bidirectional ports

 


@mcgett wrote:

You don't need anything more than a standard signal declaration to connect two bi-directional ports.

 

Hopefully, you are doing this in a test bench and not attempting to do this within a single FPGA design.


i did try a standard signal declaration and it didn't work. 

this is the problem: I am using a two directional port
(in and out). i am using this by sending data to it and receiving data
from it from another vhdl module also with a 2 directional port. Now
the problem is when it comes to connecting the module to the port;
when in the toplevel i start connecting all the modules together i
use:

fpga_pins <= module_pins

(where both fpga_pins and module_pins are bi directional)

the module can only send data, when i tell it to receive it does not work.
when i use:

 module_pins <= fpga_pins

the inverse applies.

when i use
fpga_pins <= module_pins
module_pins <= fpga_pins

it doesn't work, but i'm not sure whether it reads or writes...

with regards to your other point, no i didn't use a testbench, why?

 

thanks for the reply

 

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Explorer
Explorer
17,472 Views
Registered: ‎09-22-2010

Re: Portmapping bidirectional ports

just to make things clearer..

 

when i want to read, i set the module_pins as high impedance and then i read the port. but if the mapping is 

 

fpga_pins <= module_pins; the read won't work.

 

if i write it vice versa though it will work.

 

so i think that the problem is possibly with the port mapping given that the port mapping  doesn't seem to take into consideration that the fpga and module pins are inout.

 

thanks again

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Xilinx Employee
Xilinx Employee
17,447 Views
Registered: ‎01-03-2008

Re: Portmapping bidirectional ports

Your original post and the subsequent reply posts are described two different topologies.

 

Based on your last post, my understanding is that you have a top level design with a bi-directional port and a sub-module that sources and receives the data from this port.

 

Your top level entity should desribe this port as an "INOUT" like the following example:

    my_bidir : INOUT std_logic;

 

Your sub-module should have three ports on it like the following example

    my_dout : OUT std_logic;

    my_dtri : OUT std_logic;

    my_din  : IN  std_logic;

 

In your top level a bi-directional IO buffer should be instanatiated like the following example:

    my_iobuf : IOBUF

          port map (

           IO => my_bidir,

           O  => my_dout,

           T  => my_dtri,

           I  => my_din

          );

 

or this alternative behavioural example:

    my_bidir <= my_dout when my_dtri = '0' else 'Z';

    my_din   => my_bidir,  // On the sub-module port mapping

 

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Explorer
Explorer
17,443 Views
Registered: ‎09-22-2010

Re: Portmapping bidirectional ports

yes the system i am talking about is exactly what you said. i didn't really understand your reply though. my code looks like this. with regards to the submodule:

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- THIS MODULE WILL IMPLEMENT THE BIDIRECTIONAL PORT NEEDED
-- SO THAT THE FPGA CAN READ AND WRITE TO THE GLCD FROM THE 
-- SAME PINS.
entity GLCD_BI_DIRECTIONAL_PORT is
    Port ( GLCD_DATA_WRITE : in  STD_LOGIC_VECTOR (3 downto 0);
           GLCD_DATA_READ  : OUT  STD_LOGIC_VECTOR (3 downto 0);
           CONTROL : in  STD_LOGIC;
           GLCD_PINS : inout  STD_LOGIC_VECTOR (3 downto 0));
end GLCD_BI_DIRECTIONAL_PORT;
architecture Behavioral of GLCD_BI_DIRECTIONAL_PORT is
begin
PROCESS(CONTROL,GLCD_DATA_WRITE,GLCD_PINS)
BEGIN
IF(CONTROL = '0') THEN -- WRITE
GLCD_PINS <= GLCD_DATA_WRITE;
ELSE
GLCD_PINS <= "ZZZZ"; -- SET AS HIGH IMPEDANCE INPUT
GLCD_DATA_READ <= GLCD_PINS;
END IF;
END PROCESS;
end Behavioral;
The toplevel port is exactly as you mentioned ( GLCD_DATA : INOUT  STD_LOGIC_VECTOR (7 downto 0); )
So what exactly should i add/edit?
thanks a lot

 

Xilinx Employee
Xilinx Employee
17,435 Views
Registered: ‎01-03-2008

Re: Portmapping bidirectional ports

Your code looks fine, except that you have the GLCD_DATA_READ line in the wrong place it is should be like this.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- THIS MODULE WILL IMPLEMENT THE BIDIRECTIONAL PORT NEEDED
-- SO THAT THE FPGA CAN READ AND WRITE TO THE GLCD FROM THE
-- SAME PINS.

entity GLCD_BI_DIRECTIONAL_PORT is
    Port ( GLCD_DATA_WRITE : in    STD_LOGIC_VECTOR (3 downto 0);
           GLCD_DATA_READ  : out   STD_LOGIC_VECTOR (3 downto 0);
           CONTROL         : in    STD_LOGIC;
           GLCD_PINS       : inout STD_LOGIC_VECTOR (3 downto 0));
end GLCD_BI_DIRECTIONAL_PORT;

architecture Behavioral of GLCD_BI_DIRECTIONAL_PORT is

begin

PROCESS(CONTROL,GLCD_DATA_WRITE)
BEGIN
   IF(CONTROL = '0') THEN -- WRITE
      GLCD_PINS <= GLCD_DATA_WRITE;
   ELSE
      GLCD_PINS <= "ZZZZ"; -- SET AS HIGH IMPEDANCE INPUT
   END IF;
END PROCESS;


GLCD_DATA_READ <= GLCD_PINS;


end Behavioral;

 

--------------------------

or in a shorter form

--------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- THIS MODULE WILL IMPLEMENT THE BIDIRECTIONAL PORT NEEDED
-- SO THAT THE FPGA CAN READ AND WRITE TO THE GLCD FROM THE
-- SAME PINS.

entity GLCD_BI_DIRECTIONAL_PORT is
    Port ( GLCD_DATA_WRITE : in    STD_LOGIC_VECTOR (3 downto 0);
           GLCD_DATA_READ  : out   STD_LOGIC_VECTOR (3 downto 0);
           CONTROL         : in    STD_LOGIC;
           GLCD_PINS       : inout STD_LOGIC_VECTOR (3 downto 0));
end GLCD_BI_DIRECTIONAL_PORT;

architecture Behavioral of GLCD_BI_DIRECTIONAL_PORT is
begin

 GLCD_PINS      <= GLCD_DATA_WRITE when CONTROL = '0' else "ZZZZ";
 GLCD_DATA_READ <= GLCD_PINS;

end Behavioral;


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Explorer
Explorer
17,428 Views
Registered: ‎09-22-2010

Re: Portmapping bidirectional ports

hi,

i tried it again but it won't work at all. when i set 

 

module_pins <= toplevel pins it works, but if vice versa it won't work... the problem is in the mapping i suppose....

 

by simply connecting the toplevel with the submodule using a simple std_logic signal is not working even though it seems good...

 

thanks for your help

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Historian
Historian
17,423 Views
Registered: ‎02-25-2008

Re: Portmapping bidirectional ports

 


@bouvett wrote:

hi,

i tried it again but it won't work at all. when i set 

 

module_pins <= toplevel pins it works, but if vice versa it won't work... the problem is in the mapping i suppose....

 

by simply connecting the toplevel with the submodule using a simple std_logic signal is not working even though it seems good...

 

thanks for your help


Ed McGett's code is absolutely correct. If you are not implementing your design as he suggests, perhaps you should!

 

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
17,414 Views
Registered: ‎01-03-2008

Re: Portmapping bidirectional ports

> module_pins <= toplevel pins it works, but if vice versa it won't work

 

You provided your module code, but you didn't provide your top level code, but here is how it should look in snippets.

 

entity MY_TOP_LEVEL is
    Port ( ...             : ....
           TOP_GLCD_PINS   : inout STD_LOGIC_VECTOR (3 downto 0);
           ...             : ....
           );
end MY_TOP_LEVEL;


architecture Behavioral of MY_TOP_LEVEL is

  component GLCD_BI_DIRECTIONAL_PORT

    Port ( GLCD_DATA_WRITE : in    STD_LOGIC_VECTOR (3 downto 0);
           GLCD_DATA_READ  : out   STD_LOGIC_VECTOR (3 downto 0);
           CONTROL         : in    STD_LOGIC;
           GLCD_PINS       : inout STD_LOGIC_VECTOR (3 downto 0));
   end component;
begin


   my_bidir : GLCD_BI_DIRECTIONAL_PORT

       port map (

             GLCD_DATA_WRITE => ...,
             GLCD_DATA_READ  => ...,
             CONTROL         => ...,
             GLCD_PINS       => TOP_GCLD_PINS

               );

    ...

    ...

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Explorer
Explorer
10,253 Views
Registered: ‎09-22-2010

Re: Portmapping bidirectional ports

Thanks for the reply, the problem was solved after i mapped the module directly to the pins without using any signals in between.

 

regards

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Professor
Professor
10,251 Views
Registered: ‎08-14-2007

Re: Portmapping bidirectional ports

You might have clarified this in the original post by showing how you connect

the sub-module to the FPGA pins.  There is no direct "assignment" operator

that works bidirectionally.  So in fact the top level port, if bidirectional or "INOUT"

MUST be directly connected to the submodule port with no intervening signal

or assignment.  The only other way is to break the bidirectional signal into

input, output, and output enable signals.  If you need to do that, the top level is

the best place to do it.  Note also that you cannot connect a bidirectional

signal to more than one sub-module.  i.e. no "T" connections.  This is because

there are no internal tristate drivers in the FPGA.  So again if you need to

branch out a bus inside the FPGA you should first make the signals all

unidirectional at the top level.

 

Regards,

Gabor

-- Gabor
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Visitor agouwin
Visitor
9,995 Views
Registered: ‎10-22-2011

Re: Portmapping bidirectional ports

I'm wondering do we have to declare the sub module this way? I ran into this problem and my port for the sub module would be like this

  component GLCD_BI_DIRECTIONAL_PORT

    Port ( CONTROL         : out    STD_LOGIC;
           GLCD_PINS       : inout STD_LOGIC_VECTOR (3 downto 0));
   end component;

 

I have to do this because all the GLCD_DATA_WRITE and GLCD_DATA_READ all handled inside my submodule which has nothing do to with other module. And I will have to leave them open anyway if I declare them.


so in the submodule declaration part, I would have two signals declared as

signal GLCD_DATA_WRITE : std_logic_vector(3 downto 0);

signal GLCD_DATA_READ  : std_logic_vector(3 downto 0);

 

and then I would have the following in behavior description

 

GLCD_PINS <= GLCD_DATA_WRITE when CONTROL = '1' else (others => 'Z');

GLCD_DATA_READ <= GLCD_PINS;

 

Do you see this working? Thanks!!!

 

> module_pins <= toplevel pins it works, but if vice versa it won't work

 

You provided your module code, but you didn't provide your top level code, but here is how it should look in snippets.

 

entity MY_TOP_LEVEL is
    Port ( ...             : ....
           TOP_GLCD_PINS   : inout STD_LOGIC_VECTOR (3 downto 0);
           ...             : ....
           );
end MY_TOP_LEVEL;


architecture Behavioral of MY_TOP_LEVEL is

  component GLCD_BI_DIRECTIONAL_PORT

    Port ( GLCD_DATA_WRITE : in    STD_LOGIC_VECTOR (3 downto 0);
           GLCD_DATA_READ  : out   STD_LOGIC_VECTOR (3 downto 0);
           CONTROL         : in    STD_LOGIC;
           GLCD_PINS       : inout STD_LOGIC_VECTOR (3 downto 0));
   end component;
begin


   my_bidir : GLCD_BI_DIRECTIONAL_PORT

       port map (

             GLCD_DATA_WRITE => ...,
             GLCD_DATA_READ  => ...,
             CONTROL         => ...,
             GLCD_PINS       => TOP_GCLD_PINS

               );

    ...

    ...

------------------------------------------------------------------
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Tags (1)
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Teacher rcingham
Teacher
9,981 Views
Registered: ‎09-09-2010

Re: Portmapping bidirectional ports

"Do you see this working?"
No, because in VHDL up-to-and-including-VHDL-2002, you cannot read an output port in the associated architecture.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Professor
Professor
9,979 Views
Registered: ‎08-14-2007

Re: Portmapping bidirectional ports


@rcingham wrote:
"Do you see this working?"
No, because in VHDL up-to-and-including-VHDL-2002, you cannot read an output port in the associated architecture.

I've always seen this as an unnecessary restriction in VHDL.  Verilog does not have the same

restriction.  Generally the workaround is to use an internal signal like "CONTROL_i" for all

internal use and then assign the output like "CONTROL <= CONTROL_i" at the end of the code.

 

In Verilog you can use feedback from output ports, and even if these go to pins (for

example top level output ports) the feedback is internal, it does not actually require

an I/O buffer at the pin.  If necessary, XST will replicate registers to allow this feedback,

but it's all "under the hood" rather than explicit in your source code.  VHDL does have

the "buffer" port type which is essentially similar to the Verilog output port, in that it

allows feedback inside the module.  However I have read that this can cause other

problems, and is generally frowned upon for synthesis.

 

-- Gabor

-- Gabor
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Teacher rcingham
Teacher
9,975 Views
Registered: ‎09-09-2010

Re: Portmapping bidirectional ports

"I've always seen this as an unnecessary restriction in VHDL."
...which is removed in VHDL-2008. When the XST parser supports that is a question that I would like to know the answer to!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Visitor agouwin
Visitor
9,970 Views
Registered: ‎10-22-2011

Re: Portmapping bidirectional ports

what about

 

signal GLCD_DATA_WRITE : std_logic_vector(3 downto 0);

signal GLCD_DATA_READ  : std_logic_vector(3 downto 0);

signal CONTROL_i : std_logic;

 

 

and then I would have the following in behavior description

 

CONTROL <= CONTROL_i;

GLCD_PINS <= GLCD_DATA_WRITE when CONTROL_i = '1' else (others => 'Z');

GLCD_DATA_READ <= GLCD_PINS;

 

My main question is when the synthesizer will instantiate it to a tristate port?

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Xilinx Employee
Xilinx Employee
9,963 Views
Registered: ‎01-03-2008

Re: Portmapping bidirectional ports

agouwin,

 

You came in to the thread at the end of the discussion and it appears that you have missed some of the earlier key points.  I would suggest that you go back and re-read the first part of the thread, especially post 7.

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