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adrialex
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Registered: ‎08-05-2009

Problem regarding portmaps

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I have this code below and I can't determine why my output sum is incorrect. I'm just a beginner vhdl code programmer so I'm not quite sure about my coding. My component which is a carry look ahead adder is working fine. My only problem is that at the second instance of my component, i get a wrong output.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder is
    Port ( rst : in  STD_LOGIC;
           operandA : in  STD_LOGIC_VECTOR (7 downto 0);
           operandB : in  STD_LOGIC_VECTOR (7 downto 0);
           carry_in : in  STD_LOGIC;
           carry_out : out  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR (7 downto 0));
end adder;

architecture Behavioral of adder is
    SIGNAL count : STD_LOGIC_VECTOR(1 downto 0);
    SIGNAL temp : STD_LOGIC_VECTOR(3 downto 0);
    COMPONENT clahead_addr
    PORT(
        operandA : IN std_logic_vector(3 downto 0);
        operandB : IN std_logic_vector(3 downto 0);
        carry_in : IN std_logic;         
        sum : OUT std_logic_vector(3 downto 0);
        carry_out : OUT std_logic
        );
    END COMPONENT;
   
    --INPUTS
    SIGNAL oper_add1 : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL oper_add2 : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL oper_add3 : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL oper_add4 : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL carry_in_add : STD_LOGIC;
   
    --OUTPUTS
    SIGNAL sum_add1 : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL sum_add2 : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL carry_out_add1 : STD_LOGIC;
    SIGNAL carry_out_add2 : STD_LOGIC;
   
begin
    uut1: clahead_addr PORT MAP(
        operandA => oper_add1,
        operandB => oper_add2,
        carry_in => '0',
        sum => sum_add1,
        carry_out => carry_out_add1
    );

    uut2: clahead_addr PORT MAP(
        operandA => oper_add3,
        operandB => oper_add4,
        carry_in => carry_out_add1,
        sum => sum_add2,
        carry_out => carry_out_add2
    );

    process(rst,sum_add1,sum_add2,carry_out_add1,oper_add1,oper_add2)
    begin
        if rst = '1' then
            oper_add1 <= "0000"; oper_add2 <= "0000"; oper_add3 <= "0000"; oper_add4 <= "0000";
            sum <= "00000000";
            carry_out <= '0';
        else
                oper_add1 <= operandA(3 downto 0);
                oper_add2 <= operandB(3 downto 0);
                oper_add3 <= operandA(7 downto 4);
                oper_add4 <= operandB(7 downto 4);
                sum <= sum_add2 & sum_add1;
                carry_out <= carry_out_add2;
        end if;
       
    end process;

end Behavioral;

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barryabrown
Explorer
Explorer
5,728 Views
Registered: ‎09-11-2007

The dependency list of your process looks incorrect. This should work better:

 

process(rst,sum_add1,sum_add2,carry_out_add2,operandA.operandB)

 

 

Barry

 

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4 Replies
barryabrown
Explorer
Explorer
5,729 Views
Registered: ‎09-11-2007

The dependency list of your process looks incorrect. This should work better:

 

process(rst,sum_add1,sum_add2,carry_out_add2,operandA.operandB)

 

 

Barry

 

View solution in original post

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adrialex
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Registered: ‎08-05-2009
I would like to ask for a crash course about the sensitivity list of a process. What should and what shouldn't be included in it? 
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bassman59
Historian
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Registered: ‎02-25-2008

adrialex wrote:
I would like to ask for a crash course about the sensitivity list of a process. What should and what shouldn't be included in it? 

Simple.

 

For a synchronous (clocked) process: the only things you put on the sensitivity list are the clock and an asynchronous reset (if you use one). That is it.

 

For a combinatorial process: anything that appears on the right-hand-side of any assignment in the process must be in the sensitivity list.

 

----------------------------Yes, I do this for a living.
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barryabrown
Explorer
Explorer
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Registered: ‎09-11-2007

You can also avoid the sensitivity list by converting your combinatorial process to concurrent statements.  For example,

 

oper_add1 <= "0000" when rst = '1' else operandA(3 downto 0); 

 

The above concurrent statement is equivalent to this process:

 

process (rst, operandA(3 downto 0))

begin

  if rst = '1' then

    oper_add1 <= "0000";

  else

    oper_add1 <= operandA(3 downto 0);

  end if;

end process;

 

 

Barry

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