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Adventurer
Adventurer
2,624 Views
Registered: ‎03-27-2013

Problem with DMA-Audio Demo Project on the Nexys-Video board (I2C pins & SDK)

Hi

There is a demo project for setting up Audio Codec on the Digilent Nexys Board (Artix-7) here. After running the .tcl for project creation there are several problems:

1- The project is not compatible with Vivado 2017.4. I solved its many issues after several tries.

2- There are 6 I2C ports in the MicroBlaze block design for talking to the codec, whereas there should be 2 ports; i.e. SDA & SCL. 

          When implementing design, BitGen fails for having no pin location for 6 I2C pins.

          Why such an error exist and how should I handle it?

          Note: I have designed an IO_BUF which connects 3 pins and makes an inout connection. One for SDA and one for SCL.

3- After bit file generation with mentioned workaround (Not sure it will work), hardware handoff is not generated by VIVADO.

          I have to generate it using custom tcl commands found in the xilinx forum here.

4- After forcing export to SDK, the SDK fails to program the FPGA, and says that there is no "download.bit" file.

          Ther does exist a bit file, namely "design_1.bit", but the SDK does not build "download.bit" by combining design_1.bit and application program!

 Please help on resolving issues.

Thanks

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Adventurer
Adventurer
2,612 Views
Registered: ‎03-27-2013

As a workaround for the 4th problem, I programmed the FPGA from Vivado, and just ran the application from SDK.

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Moderator
Moderator
2,514 Views
Registered: ‎11-09-2015

Hi @msjatxilinx,

 

Could you clarify what issues you still have?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
2,461 Views
Registered: ‎03-27-2013

Thanks @florentw

My issue is no longer very important, nonetheless I want to have a clean project, which runs without any issues.

I cannot export hardware directly to SDK; i.e. without custom TCL commands. If this could be managed, so that every thing is neat, it would be better.

Is there any way to resolve such issues? 

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Moderator
Moderator
2,421 Views
Registered: ‎11-09-2015

HI @msjatxilinx,

 

I cannot export hardware directly to SDK; i.e. without custom TCL commands.

> Could you give details?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
2,397 Views
Registered: ‎03-27-2013

Thanks @florentw

After implementation, when I want to export hardware to SDK, Vivado complains that "The hardware handoff file (.sysdef) does not exist."

In order to remove this error, I have to manually generate .sysdef file using TCL commands, whenever I run synthesis.

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Moderator
Moderator
2,360 Views
Registered: ‎11-09-2015

Hi @msjatxilinx,

 

Could you try to regenerate the BD output products? It might solve this issue


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
2,292 Views
Registered: ‎03-27-2013

Thanks @florentw

Actually I always run "Generate Output Products" before implementation, yet it does not change the situation.

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Moderator
Moderator
2,289 Views
Registered: ‎11-09-2015

Hi @msjatxilinx,

 

Could you share your updated project?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
2,181 Views
Registered: ‎03-27-2013

Thanks @florentw

Actually the project archive is too large.

Is there some type of archiving similar to Quartus archive (with small size) in Xilinx?

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