First, I'm a long time microcontroller guy, and never thought I'd get as far as I have with hdl. My hat is off to Xilinx and the tools. But I'm still learning a lot.
I'm stuck on a problem right now with a simple SPI. In the code below, I can see the value of DataToWrite is not changing on my logic analyzer when I force writes from a computer program. And most of the time the output is correct. But occasionally I'll see a bit that is supposed to be a '1' in the SPIData stream instead be a zero. Behavioral simulation works as expected, and speeds are slow (12 MHz SPI clock)
There are a few clues that I don't understand, but perhaps someone else does
1) I discovered the problem when I was using ISE 11.1. When using that, writing FFFF would show some low order bits flicking to zero unexpectedly. They are correctly aligned time wise. It's just I was expecting to see a '1' there and a zero was seen instead.
3) After I moved to 11.4 tonight (hoping that might fix the problem), the location of the bits flicking to zero moved to a single bit in the higher orders.
4) If I route the DataToWrite[0] signal to the outside world, the problem goes away.
5) Diff'ing the output of the tools with DataToWrite going to the outside and not going to the outside didn't reveal any difference. I was kind of hoping to see something get optimized away when the signal wasn't getting routed to an outside pin, but no luck.
Any thoughts on what to try next? This PCB has 5 bits of easily accessed IO, and no jtag, so 32 channels of debug isn't possible. Next board will have more.
The system clock is 48 MHz. The SPI clock is running at 12 MHz. ClkDiv4 is actually running at 24 MHz. ClkDiv4 is derived by a counter driven by 48 MHz clock.
Status[0] is set/cleared by the 48 MHz clock. This is the indication to start writing.
// State machine to pump out dataalways @(posedge ClkDiv4)begin case (State) IDLE: begin if (Status[0]) begin // If set, we need to begin transmission of the data in DataToWrite TXBuf <= DataToWrite; State <= TX0; end else begin // Nothing to do SPICSReg <= 1; end end TX0: begin State <= TX1; SPICSReg <= 0; SPIClkReg <= 0; BitCounter <= 6'd32; // Each count is half a cycle, so this will transmit 16 bits SPIDataReg <= TXBuf[15]; TXBuf <= {TXBuf[30:0], 1'b0}; end TX1: begin BitCounter <= BitCounter - 1'b1; if (BitCounter > 0) begin SPIClkReg <= ~SPIClkReg; end else State <= IDLE; // Only change data on falling edge if (SPIClkReg) begin SPIDataReg <= TXBuf[15]; TXBuf <= {TXBuf[30:0], 1'b0}; end end default: State <= IDLE; endcaseend// If we don't have this going to the outside world, this doesn't work. Don't know why. What happens is the SPIData signal goes low corrupted at times. // Perhaps there is some optimization going on that isn't clear????assign debug1 = DataToWrite[0];
Thanks for any suggestions.
