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Did you mean:  1,689 Views
Registered: ‎11-09-2016

## Propagation time

Hi,

I did some calculations, if i divide this calculation into 3 or 4 cycles,simulation results coming TRUE.

If i did this calculations in 1 clock cycle, i'm getting FALSE results.

How can i calculate propagation time of this calculations? How many cycles that i need to complete and get true values?

This problem about simulation tool(Xsim) ? Or Is there possibility of works in 1 cycle in practice?(after place&route)

```            --multiply
piksX <= ratio_c*(cntX+1);--fixdt(40,16)
piksY <= ratio_r*(cntY+1);--fixdt(40,16)

--cast
piksX_fl <= piksX(39 downto 16);--u24
piksY_fl <= piksY(39 downto 16);--u24

--comparasion and assignment
if (piksX_fl>(inp_clen-1)) then
piksX_fl <= to_unsigned(0,8)&(inp_clen-1);
end if;
if (piksX_fl<1) then
piksX_fl <= to_unsigned(1,24);
end if;

if (piksY_fl>(inp_rlen-1)) then
piksY_fl <= to_unsigned(0,8)&inp_rlen-1;
end if;
if (piksY_fl<1) then
piksY_fl <= to_unsigned(1,24);
end if;

--difference
DeltaX <= piksX - shift_left(piksX_fl,16);--fixdt(40,16)
DeltaY <= piksY - shift_left(piksY_fl,16);--fixdt(40,16)

--multiply and summing
IndQ1 <= (piksY_fl-1)*inp_rlen + piksX_fl -1; --orgin
IndQ2 <= (piksY_fl)*inp_rlen + piksX_fl -1; --aşağı
IndQ3 <= (piksY_fl-1)*inp_rlen + (piksX_fl+1) -1 ; --sağ
IndQ4 <= (piksY_fl)*inp_rlen + (piksX_fl+1) -1; --sağ alt

--difference
DeltaX_comp <= shift_left(to_unsigned(1,40),16) - DeltaX;--fixdt(40,16)
DeltaY_comp <= shift_left(to_unsigned(1,40),16) - DeltaY;--fixdt(40,16)```

1 Solution

Accepted Solutions  2,254 Views
Registered: ‎11-09-2016

Hi,

I did timing analysis in Vivado to find longest delay(Logic&Route).

Then doing pipelining, i recode the state machine and i find maximum allowable frequency that the code works properly.

Best regards

3 Replies  Moderator
1,655 Views
Registered: ‎01-16-2013
Hi,

I am looking into this issue from different perspective for me this looks like issue with timing (when you say post-route simulation). In single clock cycle you might be facing some violations and results are not correct.

May I know what is your clock frequency? what is setup and hold slack?

When you are doing this operation in multiple clock cycle, you are actually dividing this logic and introducing pipe line and getting expected results (because timing is met).

Thanks,
Yash  1,627 Views
Registered: ‎11-09-2016

Yes, You're absolutely right.

I have 27MHz clock frequency and i want to do these process in 1 clock cycle. (About 38ns)

I use Zynq 7020 model. How can i say slack times before synthesis?

How can i estimate to do or not all process in 1 cycle? Can i validate also with simulation?

Thanks

Berker  2,255 Views
Registered: ‎11-09-2016

Hi,

I did timing analysis in Vivado to find longest delay(Logic&Route).

Then doing pipelining, i recode the state machine and i find maximum allowable frequency that the code works properly.

Best regards