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qizhong19920114
Adventurer
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Registered: ‎06-16-2014

Question about ODDR2

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I heard that for a spartan-6 there are no dedicated clock outputs and it is recommanded to use an ODDR2 as clock output. Feed it withclk and ~clk for C1 and C2 respectively, with a 0 and 1 respectively for D0 and D1 of the ODDR2 primitive. 

 

But we have dedicated pads that connected to global clock net, why we can use them as inputs, and can't use them as outputs?

 

What is the benefit of using ODDR2 in this senario? Why is it bad if I just wire the clock input pin to a general purpose output pin of spartan6 instead of using ODDR2? 

 

Thanks

 

 

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bassman59
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Registered: ‎02-25-2008

@qizhong19920114 wrote:

I heard that for a spartan-6 there are no dedicated clock outputs and it is recommanded to use an ODDR2 as clock output. Feed it withclk and ~clk for C1 and C2 respectively, with a 0 and 1 respectively for D0 and D1 of the ODDR2 primitive. 

 

But we have dedicated pads that connected to global clock net, why we can use them as inputs, and can't use them as outputs?


No FPGA that I am aware of has anything called a "clock output" pin. They are not needed. The dedicated pads that connect to clock resources are always inputs.


What is the benefit of using ODDR2 in this senario? Why is it bad if I just wire the clock input pin to a general purpose output pin of spartan6 instead of using ODDR2? 


the short answer is that with any reasonably recent FPGA family, you simply cannot connect a clock net to a not-clock resource. Go try it: create a small test design which connects a clock (which is toggling flip-flops and whatnot) to an output pin. The router will bork out and complain that there is no route from the clock network to the pad.

 

So the very reasonable workaround is to instantiate the output DDR flip-flop in the manner suggested, It doesn't cost you anything because all of the output pins have output DDR flops available. And as a bonus, using the ODDR flop (reasonably) guarantees that the skew between the output clock and any outputs which are synchronous to that clock is minimal. (You have to make sure that all of those data outputs use the flop in the IOB and not the fabric.)

----------------------------Yes, I do this for a living.

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bassman59
Historian
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17,027 Views
Registered: ‎02-25-2008

@qizhong19920114 wrote:

I heard that for a spartan-6 there are no dedicated clock outputs and it is recommanded to use an ODDR2 as clock output. Feed it withclk and ~clk for C1 and C2 respectively, with a 0 and 1 respectively for D0 and D1 of the ODDR2 primitive. 

 

But we have dedicated pads that connected to global clock net, why we can use them as inputs, and can't use them as outputs?


No FPGA that I am aware of has anything called a "clock output" pin. They are not needed. The dedicated pads that connect to clock resources are always inputs.


What is the benefit of using ODDR2 in this senario? Why is it bad if I just wire the clock input pin to a general purpose output pin of spartan6 instead of using ODDR2? 


the short answer is that with any reasonably recent FPGA family, you simply cannot connect a clock net to a not-clock resource. Go try it: create a small test design which connects a clock (which is toggling flip-flops and whatnot) to an output pin. The router will bork out and complain that there is no route from the clock network to the pad.

 

So the very reasonable workaround is to instantiate the output DDR flip-flop in the manner suggested, It doesn't cost you anything because all of the output pins have output DDR flops available. And as a bonus, using the ODDR flop (reasonably) guarantees that the skew between the output clock and any outputs which are synchronous to that clock is minimal. (You have to make sure that all of those data outputs use the flop in the IOB and not the fabric.)

----------------------------Yes, I do this for a living.

View solution in original post