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11,253 Views
Registered: ‎03-31-2015

Random Gated Clock warning

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I dont know how to fix this gated clock issue because sometimes it gives me an error and sometimes it doesn't and I can't reproduce the warning on purpose.

 

I am using the following piece of code:

 

 

----------------------------------------------------------------------------
sig_M_CLK_FREQ <= std_logic_vector(to_unsigned(M_CLK_FREQ,32));

prescaler <= "000000" & sig_M_CLK_FREQ(31 downto 25) when SET_SCLK_FAST = '1'  --16.7MHz
		   else sig_M_CLK_FREQ(31 downto 19) when SET_SCLK_FAST = '0'; --262kHz

SCLK_chip <= sig_SCLK_int;

process(SYSTEMCLK,SCLKGENERATOR_EN)
variable internal_count : integer := 0;
begin
	
	-- SCLK generator
	if SCLKGENERATOR_EN = '0' then
		internal_count := 0;
		edge_count 		<= (others => '0');
	else
		if rising_edge(SYSTEMCLK) then
			internal_count := internal_count+1;
			if internal_count >= prescaler then
				sig_SCLK_int   <= not sig_SCLK_int;
				edge_count     <= edge_count+1;
				internal_count := 0;
			end if;
		end if;
	end if;

end process;
----------------------------------------------------------------------------

 

the error I am getting sometimes:

 -- Ok I'm not getting it anymore as I was writing this, what could that be?

 It was saying something about clock net sig_SCLK_int inv

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1 Solution

Accepted Solutions
Highlighted
Instructor
Instructor
20,367 Views
Registered: ‎08-14-2007

Re: Random Gated Clock warning

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The problem is that you are using the "clock" to directly drive a pin, and possible for other logic loads as well as for clocking internal FPGA components.  If you want to drive a globally buffered clock off-chip, you should use an ODDR as a "clock forwarder."  Search for "clock forwarding" for lots of information about this.

 

For really slow clocks like yours, it's usually best to run the "guts" of the FPGA with a clock enable and just re-create the "clock" of the required phase for the output pin to the SD card.  For that you would not need an ODDR.  You could even produce the output clock the way you're doing it now, but you should not use that signal as a clock inside the FPGA.  In fact it would be best to force the clock output into an IOB flip-flop.  That gives it predictable timing from build to build.  Then if you also force any data outputs into the IOB flops as well, your clock to data skew will also remain constant from build to build.

 

What I would typically do for a slow interface like this, is to have a counter than counts up for one full output clock period and then resets to 0.  Then I would create a single cycle enable for the FPGA's internal state logic, for example on for one clock cycle when the output clock is driven high.  That gives a single internal high-speed clock cycle delay after the external rising clock edge to provide hold time for data outputs.  I would also generate a single cycle pulse active on the cycle before the external clock is driven high.  This enables the flip-flops that capture data coming from the external device.  Those flops will then sample just under one external clock period after the rising edge of the output clock for maximum system setup time, while not requiring any hold time from the external device.

-- Gabor
13 Replies
Scholar pratham
Scholar
11,245 Views
Registered: ‎06-05-2013

Re: Random Gated Clock warning

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@marijnvantricht If you are using vivado, you should not get any error for using gated clock. You can enable the gated clock conversation in vivado synthesis settings as well.

-Pratham

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11,243 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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I am not using vivado but the ISE webpack but could I just ignore that warning?

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11,236 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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I am getting the error again and by design is going bust.

PhysDesignRules:372 - Gated clock. Clock net SCLK_int_inv is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
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Moderator
Moderator
11,218 Views
Registered: ‎01-16-2013

Re: Random Gated Clock warning

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Hi,

ISE wont support clock gating conversion automatically.

The warning indicating that there might be some issue due to this type of usage. As you are using gated clock using LUT tool is saying use CE pin of FF.

This may cause you timing violation. So re-look into design and check how you can modify.
Refer clocking user guide for specific device which you are targeting

Thanks,
Yash
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Instructor
Instructor
11,196 Views
Registered: ‎08-14-2007

Re: Random Gated Clock warning

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It would seem from your code that the clock signal is generated by a flip-flop, and not combinatorial logic.  The only reason I can see for the error to come or go "randomly" is that you have allowed "register balancing" and somehow the clock signal has been "balanced" such that the gating is after the flops.  If that happens, you could end up with glitches which cause the design to fail in hardware, in addition to the warnings.

 

Taking the suggestion of the warning, you should avoid this by using a clock enable intead of a clock for the downstream logic.  That would mean making a signal that goes high for one SYSTEMCLK cycle for each full desired period of the downstream "clock" rather than generating a 50% duty cycle clock.  Then run all downstream logic using SYSTEMCLK as the clock and this single-cycle pulse as the clock enable.

 

If you don't want to take the suggestion from the warning, you might want to instantiate a BUFG after the signal sig_SCLK_int instead of just assigning it directly to SCLK_chip.  That might help the tools determine that your slow clock should not be register balanced to create a gated clock.

-- Gabor
11,181 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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it's a good idea to make a pulse rather than a slow clock, only I am making this for a SD card and I don't know how well it will respond to that. I will try the BUFG methode. Thanks for all the responds on my question so far.

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11,171 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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ERROR:Place:1205 - This design contains a global buffer instance,
   <IC1/BUFG_inst1>, driving the net, <CHIP_SD_SCLK_OBUF>, that is driving the
   following (first 30) non-clock load pins off chip.
   < PIN: CHIP_SD_SCLK.O; >
   This design practice, in Spartan-6, can lead to an unroutable situation due
   to limitations in the global routing. If the design does route there may be
   excessive delay or skew on this net. It is recommended to use a Clock
   Forwarding technique to create a reliable and repeatable low skew solution:
   instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
   Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
   .C1. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue. Although the net
   may still not route, you will be able to analyze the failure in FPGA_Editor.
   < PIN "IC1/BUFG_inst1.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1136 - This design contains a global buffer instance,
   <IC1/BUFG_inst1>, driving the net, <CHIP_SD_SCLK_OBUF>, that is driving the
   following (first 30) non-clock load pins.
   < PIN: CHIP_SD_SCLK.O; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "IC1/BUFG_inst1.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

I've looked also in the design strategy and register balancing is turned off (I got the standard xilinx default as design strategy)

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Highlighted
Instructor
Instructor
20,368 Views
Registered: ‎08-14-2007

Re: Random Gated Clock warning

Jump to solution

The problem is that you are using the "clock" to directly drive a pin, and possible for other logic loads as well as for clocking internal FPGA components.  If you want to drive a globally buffered clock off-chip, you should use an ODDR as a "clock forwarder."  Search for "clock forwarding" for lots of information about this.

 

For really slow clocks like yours, it's usually best to run the "guts" of the FPGA with a clock enable and just re-create the "clock" of the required phase for the output pin to the SD card.  For that you would not need an ODDR.  You could even produce the output clock the way you're doing it now, but you should not use that signal as a clock inside the FPGA.  In fact it would be best to force the clock output into an IOB flip-flop.  That gives it predictable timing from build to build.  Then if you also force any data outputs into the IOB flops as well, your clock to data skew will also remain constant from build to build.

 

What I would typically do for a slow interface like this, is to have a counter than counts up for one full output clock period and then resets to 0.  Then I would create a single cycle enable for the FPGA's internal state logic, for example on for one clock cycle when the output clock is driven high.  That gives a single internal high-speed clock cycle delay after the external rising clock edge to provide hold time for data outputs.  I would also generate a single cycle pulse active on the cycle before the external clock is driven high.  This enables the flip-flops that capture data coming from the external device.  Those flops will then sample just under one external clock period after the rising edge of the output clock for maximum system setup time, while not requiring any hold time from the external device.

-- Gabor
11,140 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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Okay, I want to recreate all of my clocks now but I still am a bit unclear on what should be the best approach.

 

So whats the best way to:

generate one cycle enable?

generate a SCLK signal with a 50% duty cycle?

with or without buffers (data and clock) or clock forwarders?

 

the code that I have now without any warning (appart from synthesize):

-- haha well I wanted to say that but ofcourse I get a warning now out of blue that it I am using a 9K ram block. anyway

 

 

----------------------------------------------------------------------------
sig_M_CLK_FREQ <= std_logic_vector(to_unsigned(M_CLK_FREQ,32));

prescaler <= "000000" & sig_M_CLK_FREQ(31 downto 25) when SET_SCLK_FAST = '1'  --16.7MHz 
		   else sig_M_CLK_FREQ(31 downto 19) when SET_SCLK_FAST = '0'; --262kHz

SCLK_chip <= sig_SCLK_int;
SCLK_int  <= sig_SCLK_int;

sig_SCLK_int <= sig_SCLK_int_gen when SCLKGENERATOR_EN = '1';

process(SYSTEMCLK,SCLKGENERATOR_EN)
variable count_cycle1   : std_logic := '0';
variable internal_count : integer   := 0;
begin
	
		if rising_edge(SYSTEMCLK) then					
			internal_count := internal_count+1;
			
			if internal_count >= prescaler then	
				if sig_SCLK_int_gen = '1' then
					SINGLE_CYCLE_EN <= '1';
				else
					SINGLE_CYCLE_EN <= '0';
				end if;
				
				if SCLKGENERATOR_EN = '0' then
					edge_count <= (others => '0');
				else
					edge_count <= edge_count+1;
				end if;
				
				sig_SCLK_int_gen <= not sig_SCLK_int_gen;
				internal_count   := 0;
			else
				SINGLE_CYCLE_EN <= '0';
			end if;			
		end if;

end process;
----------------------------------------------------------------------------

----------------------------------------------------------------------------
index_x_count_even <= to_integer(unsigned(edge_count(31 downto 4)));
index_y_count_even <= 7 - to_integer(unsigned(edge_count(3 downto 1)));

process(SYSTEMCLK, SINGLE_CYCLE_EN)
variable argument_count : integer range 1 to 6  := 1;
variable TIME_OUT       : integer range 0 to 31 := 0;
variable WAIT_RESP	: integer range 0 to 63 := 0;
begin
	
	if SINGLE_CYCLE_EN = '1' then
		if rising_edge(SYSTEMCLK) then		
			case STATE is

 

As you can see in the simulation is the problem I have now is that the single cycle enable, enables the rising edge one cycle too late.

 

I think it's because SINGLE_CYCLE_EN is created on the rising edge of SYSTEMCLK but I don't know how to change this.

 

Thanks for all the tips so far.

trigger-simulation-sdcardtest-fast-6-4-2015.png
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9,053 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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sorry for posting so many posts, but I thought I fixed it with the following code which works in simulation very well, but gives me the warning (following after the code).

 

 

----------------------------------------------------------------------------
sig_M_CLK_FREQ <= std_logic_vector(to_unsigned(M_CLK_FREQ,32));

prescaler <= "000000" & sig_M_CLK_FREQ(31 downto 25) when SET_SCLK_FAST = '1'  --16.7MHz 
		   else sig_M_CLK_FREQ(31 downto 19) when SET_SCLK_FAST = '0'; --262kHz

SCLK_chip <= sig_SCLK_int;
SCLK_int  <= sig_SCLK_int;

sig_SCLK_int <= sig_SCLK_int_gen when SCLKGENERATOR_EN = '1' else '0';

process(SYSTEMCLK,SCLKGENERATOR_EN)
variable count_cycle1   : std_logic := '0';
variable internal_count : integer   := 0;
begin
	
		if rising_edge(SYSTEMCLK) then					
			internal_count := internal_count+1;
			
			if internal_count >= prescaler then	
				if sig_SCLK_int_gen = '1' then
					SINGLE_CYCLE_EN <= '0';
				else
					SINGLE_CYCLE_EN <= '1';
				end if;
				
				if SCLKGENERATOR_EN = '0' then
					edge_count <= std_logic_vector(to_unsigned(1,32));
				else
					edge_count <= edge_count+1;
				end if;
				
				sig_SCLK_int_gen <= not sig_SCLK_int_gen;
				internal_count   := 0;
			else
				SINGLE_CYCLE_EN <= '0';
			end if;			
		end if;

end process;
----------------------------------------------------------------------------

 

 

 

WARNING:PhysDesignRules:372 - Gated clock. Clock net CHIP_SD_SCLK_OBUF is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.

 

CHIP_SD_SCLK is tied to SCLK_chip

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Instructor
Instructor
9,041 Views
Registered: ‎08-14-2007

Re: Random Gated Clock warning

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It seems that "CHIP_SD_SCLK" is driving clock loads.  Are you still using an ODDR clock forwarder?

-- Gabor
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9,033 Views
Registered: ‎03-31-2015

Re: Random Gated Clock warning

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The last warning was because of

 

sig_SCLK_int <= sig_SCLK_int_gen when SCLKGENERATOR_EN = '1' else '0';

 

the ( else '0' ) because the clock pin is then loaded with a normal load (not clock load) I gues.

 

So I've tried something different now.

Still got no clock forwarders or whatsoever in this design.

The thing is now I got no warnings and it works in simulation but I still can't write to the SD card, SD card is giving no error and all the responds is normal only the data isn't saved on the card.

 

the code I have now:

 

----------------------------------------------------------------------------
sig_M_CLK_FREQ <= std_logic_vector(to_unsigned(M_CLK_FREQ,32));

prescaler <= "000000" & sig_M_CLK_FREQ(31 downto 25) when SET_SCLK_FAST = '1'  --16.7MHz 
		   else sig_M_CLK_FREQ(31 downto 19) when SET_SCLK_FAST = '0'; --262kHz

SCLK_chip <= sig_SCLK_int;
SCLK_int  <= sig_SCLK_int;

sig_SCLK_int <= sig_SCLK_int_gen;

process(SYSTEMCLK,SCLKGENERATOR_EN)
variable count_cycle1   : std_logic := '0';
variable internal_count : integer   := 0;
begin
	
		if rising_edge(SYSTEMCLK) then								
			if (internal_count+1) = prescaler then	
				SINGLE_CYCLE_EN <= '1';
			else
				if prescaler = 0 then
					SINGLE_CYCLE_EN <= '1';
				else
					SINGLE_CYCLE_EN <= '0';
				end if;
			end if;
			
			if internal_count = prescaler then	
				if SCLKGENERATOR_EN = '0' then
					edge_count <= std_logic_vector(to_unsigned(1,32));
					sig_SCLK_int_gen <= '0';
				else
					edge_count <= edge_count+1;
					sig_SCLK_int_gen <= not sig_SCLK_int_gen;
				end if;
				internal_count := 0;
			else
				internal_count := internal_count+1;
			end if;		
		end if;

end process;
----------------------------------------------------------------------------

 

Is this considered as a good code?

I just want it to be as good as it can be.

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Historian
Historian
8,967 Views
Registered: ‎02-25-2008

Re: Random Gated Clock warning

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I don't see any code that involves the signal about which the tools are throwing the warning.

----------------------------Yes, I do this for a living.
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