01-09-2014 07:16 AM
I am in the early phase of a system design and I wonder how to make a smart design for future firmware upgrades. I plan to build a system with a Spartan 6 or Artix FPGA but there will also be a BeagleBone (Arm-based Linux controller) in the system. Now, I would like the FPGA to load its configuration from a flash (SPI or BPI, doesn't matter) at boot, as usual but I would also like to be able to reprogram the flash using the BeagleBone.
I have read XAPP583 which talks about how a microprocessor can reprogram the FPGA (not the flash).
I have read XAPP1146 which talks about how a microblaze inside the FPGA can reprogram the flash.
I have read XAPP058 which talks about how an external embedded controller can reprogram the FPGA (and flash?) using the JTAG ports.
I have considered connecting the CPU to the SPI port of the flash directly, or via muxes but is that the best way to do it?
Has anyone done this and would like to share some experience?
01-09-2014 09:53 AM
I did this with a V4, but that doesn't matter. I hung an SPI flash off of an 8051. The SPI flash was programmed by the 8051, with the firmware image coming in over UART. The FPGA uses slave serial configuration and the micro would simply read the image from the SPI EEPROM and bit-bang the data to the FPGA. The micro is responsible for driving PROGRAM_B and INIT_B as well as monitoring INIT_B and DONE.
01-09-2014 12:19 PM
I have also done something similar, with a Spartan 6.
In this system, the S6 is Master of an SPI memory and the PROG_B line is controlled by a micro (LC1114, I think) at start up (the micro also controls a digital power circuit that supplies the FPGA). A host CPU - ComEx board with an Intel Atom running VxWorks - has an FPGA image (different to the one in the SPI memory) and transfers data, over a PCIe link, to the FPGA which, in turn, writes the data into the SPI memory, page by page. The FPGA can then request reconfiguration from the micro over a second dedicated SPI comms channel. This system uses the multiboot feature of the FPGA.
It seemed like a good idea at the time but now I write it down, it seems rather complicated! It works perfectly, though. Just for info, the entire write-to-reconfigure sequence takes about 10 seconds using an LX25T, and includes a data verification sequence.