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Explorer
Explorer
6,330 Views
Registered: ‎08-23-2011

Reg: xilinx XA2C128 CPLD user IO pins ... some queries?

hi,

 

i am working with the xilinx XA2C128 CPLD (compiling in ISE 14.1). i've read the data sheet and this cpld has about 80 user IOs. out of these IOs, some are  GTS = global output enable, GSR = global reset/set, GCK =global clock, CDRST = clock divide reset etc.

my questions are - 

 

1) i know the GSR, GCK, GTS pins can be used as general purpose IOs.

but i wanted to know if the other general purpose IOs can be used as clock input into the CPLD? or is there some restriction that only GCK lines can be used to input clocks into the CPLD design?

 

2) there is a GSR pin in the CPLD. shoudl the main design reset input signal be mapped to this pin in particular or can it go onto any general purpose IO?

 

3) the datasheet for this cpld (DS554) says there is optional bus-hold or weak pull-up on some select IO pins. however the datasheet does not specify whcih pins. can someone please shed some light on which pins would have the weak p.u.?

 

please let me know ...

 

thanks,

z.

 

 

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1 Reply
Moderator
Moderator
6,294 Views
Registered: ‎01-15-2008

Re: Reg: xilinx XA2C128 CPLD user IO pins ... some queries?

Global clock, global output enable, and global set/reset CPLD control signals can be implemented either on special globally routed nets (GCK, GTS, GSR) or as ordinary signals through p-terms. Control signals assigned to global nets are faster and do not use function block resources.

 

check for more info on this here

http://www.xilinx.com/itp/xilinx10/isehelp/ise_r_comp_gck_gts_gsr.htm

 

for the cpld i/o details check the following which should help

http://www.xilinx.com/support/documentation/user_guides/ug445.pdf

 

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