UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,495 Views
Registered: ‎07-28-2011

Regarding : Caught standard exception

Hi,

 

I am using ise 10.1

 

I am using system generator 10.1

I am designing a small design using fir compiler 4.0.

 

When i simulate the design, it is working without showing any erors.

 

But, when i try to generate HDL Netlist,

it shows an error as :

 

----------------------------------------------------------------------------------------------------

Summary: caught standard exception.

 

standard exception: XNetlist Engine:

An exception was raised:

 

com.xilinx.sysgen.netlist.NetlistInternal: expected to find

C:/netlist/sysgen/core_io6j/coregen_tmp/fir_compiler__virtex4_4_0_4b41f689bf97c0cl_flist.txt at 

               C:\netlist\sysgen\masterScript55573.pl line 821

 

Reported by

Unspecified

----------------------------------------------------------------------------------------------------

 

What might went wrong.?

0 Kudos