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jwizard93
Observer
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Registered: ‎06-07-2016

Replacing Altera asyncram component using Vivado Block Generator (8.2) in porting project.

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Hello,

 

Brand new to this community and largely new to FPGAs so I hope I'm not disruptive as I post my question.

 

My question: How can I recreate a memory block which was made using Altera's "asyncram" Megafunction?

 

I am attempting to port an FPGA implementation of a neural net created with Quartus into something I can load onto a Virtex-7 device using Vivado.

 

Everything was going very smoothly as the majority of the project is in verilog and system verilog. I was simply adding the source files into a Vivado project. Now I'm stuck trying to make a memory module work.

 

I attempted to use the Block Generator (8.2) which I accessed with the IP Catalog's "Block Memory Generator" under "RAMs and ROMs." My intent was to attempt to recreate the same module as best I could and learn from the output errors received after clicking "Open Eleborated Project" in the Flow Navigator.  However, I haven't progressed in quite some time. The errors are related to the fact that instances of my memory blocks don't have the right port names. These names here taken from the verilog that instantiates a block:

 

altsyncram	altsyncram_component (
				.address_a (address),
				.clock0 (clock),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_a ({32{1'b1}}),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_a (1'b0),
				.wren_b (1'b0));

In the block generator it seems like I have port names that are different. For example "addra" instead of "address_a"

Also I do not believe that I'm creating the exact same idea because I don't have this number of ports, so I'm afraid I'm not exactly asking a very specific question as much as I'm looking for advice on how to handle this situation:

 

Recreating an Altera asyncram Megafunction generated memory module in Vivado.

 

Thank you very much if you find the time to read this and provide help.

 

Much Appreciated.

 

 

 

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austin
Scholar
Scholar
9,648 Views
Registered: ‎02-27-2008

Look at:

 

ug1192.pdf Xilinx Design for Altera Users:

 

https://encrypted.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0ahUKEwjq1ZyP5ZbNAhVcVWMKHd0xDyMQFggbMAA&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fug1192-xilinx-design-for-altera.pdf&usg=AFQjCNE2swptEb9iri0A0e...

 

It has become so popular (to switch) that we had to create this guide.

 

Feel free to use these forums, and thank you,

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
Scholar
Scholar
9,649 Views
Registered: ‎02-27-2008

Look at:

 

ug1192.pdf Xilinx Design for Altera Users:

 

https://encrypted.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0ahUKEwjq1ZyP5ZbNAhVcVWMKHd0xDyMQFggbMAA&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fug1192-xilinx-design-for-altera.pdf&usg=AFQjCNE2swptEb9iri0A0e...

 

It has become so popular (to switch) that we had to create this guide.

 

Feel free to use these forums, and thank you,

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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jwizard93
Observer
Observer
5,321 Views
Registered: ‎06-07-2016
Thank You very much. The documentation quickly led me towards an elaborated design. Whether it is a correct design remains to be seen but I think I'm through this hurdle.
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Anonymous
Not applicable
4,015 Views

Hi,

 

I have the same issue.

Did you find a solution? If so, please share.

 

Thx.

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