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Explorer
Explorer
5,241 Views
Registered: ‎04-07-2013

Rule violation gpio have no routable drivers!

Hi,

 

What I did was to add some set_property LOC constraints, then these errors happen during generating bitstream, and stopped with error

 

 

In Vivado Messeges:

 

 58 net(s) have no routable drivers. The problem bus(es) and/or net(s) are

*/gpio_pin/OUT

*/gpio_pin/OUT

....

*/gpio_pin/OUT

*/gpio_pin/OUT

*/gpio_pin/OUT (the first 15 of 58 listed).

 

 

 

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6 Replies
Xilinx Employee
Xilinx Employee
5,193 Views
Registered: ‎09-20-2012

Hi @bowen_fu

 

Open Implemented design and check what are the drivers and loads of these nets.

Thanks,
Deepika.
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Community Manager
Community Manager
5,184 Views
Registered: ‎07-23-2012

Are you targeting Zynq? If yes, please make sure that you enabled GPIO EMIO if the defined LOC constraints are on PL side. By default, GPIO MIO is choosen.
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Explorer
Explorer
5,175 Views
Registered: ‎04-07-2013

 

It turns out to be tool bugs!!!

 

Vivado stops with error when generating bitstream.

We rerun the Generate Bitstream, then it passes.

 

What is that......

 

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Explorer
Explorer
5,137 Views
Registered: ‎04-07-2013

Does synopsys synplify perform better?
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Moderator
Moderator
5,071 Views
Registered: ‎07-23-2015

@bowen_fu Can you post  more details like Viavdo version, Part you are using and the log files runme.log & *.vdi files.  

 

This will help to look into the issue. 

 

Also, can you check what happens if you open routed.dcp file & run command: write_bitstream the first time

- Giri
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Community Manager
Community Manager
4,986 Views
Registered: ‎07-23-2012

This looks odd. If the errors during generate bitstream are genuine, we should hit the error every time.

Can you please compare the generate bitstream log in both cases (working & not-working) to find the differences?
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