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08-05-2011 06:14 PM
Hello,
My question regards the SPARTAN-6 FPGA PLL device.
I am developing a project that uses PLL, which is rives with one of its output clocks to a BUFPLL device.
When implementing the design, the PAR (Place And Route) tool fails to route the design.
The error message is the following:
Unroutable signal: CLKx10_sig pin: my_interface/my_interface/ioclk_buf/PLLIN
In essence, the output clock from the PLL (signal CLKx10) cannot be routed to the BUFPLL (ioclk_buf).
I verified in the SPARTAN-6 CLOCK RESOURCES GUIDE that the two cites (PLL and BUFPLL) can be
routed together, so this is not the problem.
As far as I understand, the PLL output clock should be connected directly to the BUFPLL input port (PLLIN).
What am I doing wrong here?
Can someone advise me what to do?
Thanks,
Abie Anaton
08-05-2011 06:33 PM
The Spartan-6 has an interesting set of interconnect resources.
Please list all of your clocks, and how they are buffered, and any constraints you have placed on those clocks and bufffers. You may be exeeding your buffer budget, or you may have run out of interconnect.
-- Bob Elkind
08-07-2011 03:44 PM
Hello again,
I run the following clocks:
1 - the PLL input clock (CLOCKIN) is routed from an external clock pad through a BUFIO buffer.
2 - the PLL output clock (CLOKOUT) drives the FPGA logic and is routed with a BUFG buffer.
3- the PLL second output clock (CLOCKOUT1) is connected to a BUFPLL primitive (GCLK port) and is routed with a BUFG.
4- the PLL third clock (CLOCKOUT2) is connected directly to a BUFPLL primitve (PLLIN port)
My design implements a DVI transmission (Tx) controller. I take a pre-defined pixels data and transmit them using
a DVI encoder outside to the TDMS FPGA ports, which in turn are connected in my board to an external cable port.
Any advice to my problem will be helpful. Thanks
Regards,
Abie
08-07-2011 05:41 PM - edited 08-07-2011 05:42 PM
I'm guessing that this is the clock signal which isn't routing.
4- the PLL third clock (CLOCKOUT2) is connected directly to a BUFPLL primitve (PLLIN port)
Here's a suggestion:
"Comment out" the pin assignments for the TMDS output pins which are driven by the BUFPLL/OSERDES2 blocks. Let the ISE tools auto place these pins. I guessing that the pins assignments for these TMDS outputs may be the underlying interconnect problem. Of course, the location of the BUFPLL must be unconstrained as well. See it the map/place/route processes complete successfully.
Just a guess.
-- Bob Elkind
08-08-2011 05:32 AM
Hello Bob,
Your guess is right, the BUFPLL PLLIN input port signal is the one that the PAR tool cannot route.
Unfortunately, I cannot comment out the TDMS FPGA pins, as their locations are dictated by me by the SPARTAN-6 FPGA
ATLYS board (Digilent Inc.).
However, I verified that the PLL buffer primitive location cite complies with my PLL primitive location (by reading
table 3-1 in the SPARTAN-6 clocking resources guide).
I have a question, though:
1 - Are their any limitations about which PLL output clock ports can be routed to a BUFPLL primitive?
Is it possible that I routed a non-allowed CLOCKOUT port to the BUFPLL input PLLIN port?
Best Regards,
Abie
08-08-2011 05:40 AM - edited 08-08-2011 03:21 PM
Are their any limitations about which PLL output clock ports can be routed to a BUFPLL primitive?
Is it possible that I routed a non-allowed CLOCKOUT port to the BUFPLL input PLLIN port?
BINGO! You found the problem.
From UG382 page 96:
BUFPLL and BUFPLL_MCB input clocks can be connected to either CLKOUT0 or CLKOUT1 from the PLL.
An example of a not-entirely-useful error message.
-- Bob Elkind
08-08-2011 03:04 PM
Thanks Bob.
You really helped me solve it.
I'll look into it soon and give you a feedback if it will be solved.
Best Regards,
Abie
08-12-2011 02:28 PM
Hello Bob,
I made the changes we discussed upon, and indeed the problem was solved.
I was able to synthesize the project with the ChipScope project, and now I'm prepared to check the design.
I now hope that my design will be able to drive the DVI data through the board's connectors outside in the correct manner.
Thank you again for your kindly help and support.
Regards,
Abie Anaton
09-16-2011 12:09 AM
hello
I want to run a simple programe on spartan 6 (I work with ise 12.3)
and I don't know what need to be connected (which cables).
do I need anyway 2 cables of USB?
please write in detail.
thank you
09-16-2011 01:05 AM
laxus,
Please start a new thread. When multiple topics are discussed in a single thread, it makes a mess of both discussions.
-- Bob Elkind