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Newbie
7,738 Views
Registered: ‎06-03-2015

## Safe-deposit Box designing

Hello guys,

I am a beginner in verilog programming and i need some help from you in a program. I need to project an automatic order for a safe-deposit box.The code has 4 decimal digits.The code is entered when you close the locker,and you need to enter it another time for verification.The code is held as a key.When enter the key the safe-box is opened and the code resets(you need again to put a new cod and verify it again in order to lock the safe-box).The error is shown only when we enter the 4 letters(no verification on each one). In the initial phase the safe-deposit box is locked and we know the key(4digit code).

I started trying to do something and i thought at:

Putting 4 paramaters:  parameter N1=0,N2=0,N3=0,N4=0 each one means one of the digit from the code.

For that i may need some states: q0(state)-The safe-deposit box is LOCKED.

And 4 states(s1,s2,s3,s4) each verifying each digit,if for example the digit is wrong in the S2,we jump to a error state E3.(3 because the error state for q0 is E1). I wrote this code

reg state,next_state

always @(posedge clk)

state<=next_state:

always @(*)

case(state)

.......

S2:next_state=(x==N3)?S3

.......

E2:next_state=E3;

assing y=(state==S4)   S4 is the state when the deposit box is OPENED.

I hope someone will try to help me in order to solve this.Thanks!

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2 Replies
Instructor
7,706 Views
Registered: ‎08-14-2007

## Re: Safe-deposit Box designing

I'm not sure what your question is.  However I don't think you want to use parameters for the code.  That's because a parameter will only change when you re-synthesize.  I assume you want to be able to change the code while the FPGA is actually running (from your description).  So then the unlocking module would need to take the code as inputs rather than parameters.  You would have some sort of locking module to set the code, I assume.  There are probably hundreds of ways to do this.

Another thing about state machines...  You might want to forget the two-process state machine and do it all in a single clocked process.  Search the forums for "two process state machine" to see how easy it is to get in serious trouble with them.  So unless your instructor has clearly spelled out that you must use a two-process FSM, I would start getting used to designing an FSM in a single clocked process.

-- Gabor
Newbie
7,668 Views
Registered: ‎06-03-2015

## Re: Safe-deposit Box designing

I dont want to use on the FPGA ,i want it only to work as a program(i can re-synthesize it whenever i change my code).I can do the program how do i want,there are no restrictions.I didint had a question,i wanted some tips to make the program do what i wrote in the description(some line codes,because i am a beginner and i didint find these kind of programs on the internet).