08-06-2018 11:06 AM
I need help choosing an FPGA chip that will work with
analogue-to-digital converter via LVDS bus.
The transmitter will be clocked at min. 250 MHz, so and data are
displayed with this clock on the LVDS bus.
The ADS4126IRGZT transducer was pre-selected, but it is slightly too
slow, probably choose another one, faster.
The FPGA system is designed to read min. 100,000
subsequent measurements to the memory and then forward them to
What FPGA can I implement such functionality?
08-06-2018 02:14 PM
Here’s one way to view your requirements and select an FPGA:
1) I/O pin requirement (~14 LVDS pairs + 6 singles): I find that the ADS4126IRGZT is 12-bit. So, you need 12 LVDS pin-pairs on the FPGA. You’ll probably also need another 2 LVDS pin-pairs for clocks in/out and 6 more single-pins for other stuff (setup serial interface etc).
2) Storage requirement (1.2Mb BRAM): You can store the 100,000 samples in block-RAM(BRAM). So, the FPGA needs at least 100,000 x 12bit = 12.Mb storage capacity.
3) Storage speed (250 MHz): Samples (12-bit) will be collected at a rate of 250MHz and will need to be stored at the same rate.
4) Development Software (Vivado): Do you plan to purchase (at ~$3K/yr) the Vivado software/support or go with the free-of-charge Vivado WebPACK software (and no support except via this Forum)?
I recommend looking at the 7-Series family of Xilinx FPGAs (Artix-7, Kintex-7, Virtex-7). My personal favorite is the Kintex-7, which offers a nice tradeoff between cost and performance.
Assuming you select the Kintex-7 and you want to use the free-of-charge Vivado WebPACK software, then you can start your search in Xilinx document ug973 (see Table 2-1). There you will find a list of the Kintex-7 FPGAs (XC7K70T and XC7K160T) supported by Vivado Webpack.
Next, go to Xilinx document ds180 for the 7-Series. Tables 6 and 7 in this document show some capabilites of the XC7K70T and the XC7K160T: 4.8Mb and 11.7Mb of BRAM, 300 and 400 I/O (for FBG676 package size). So, both of these devices satisfy your requirements for I/O pins and BRAM storage.
Next go to Xilinx document pg058 for BRAM. For various BRAM configurations, Chapter 2 of pg058 shows operating frequency – all above your 250MHz requirement (some pipelining may be needed).
08-06-2018 04:46 PM
If I may suggest, getting a board, either a module as you suggest or an evaluation board like the KCU116 is a good way to start. Design of an Ultrascale board, with its power supplies, interfaces, board layout and possibly external memory on top of a high speed ADC interface and whatever computer interface is used can be a bit much unless you have a development team with some experience.
I would also shy away from trying to capture all of the data in BRAM. Deeply cascaded BRAM may not make timing at 250MHz. UltraRAM or external DDR3 or DDR4 connected to the FPGA fabric may be a better bet.
08-06-2018 07:05 PM
I agree with Bruce that creating you own FPGA board can be a big challenge – especially if you use external RAM with DDR3 or DDR4 interfaces.
I’m not sure I agree with Bruce’s suggestion to use the Kintex-Ultrascale FPGA, which is quite a different animal than the Kintex-7. The KCU116 board mentioned by Bruce uses the XCKU5P-2FFVB676E FPGA. This FPGA is currently selling for $2257 at digikey.com – more than 7x the cost of the XC7K160T-1FBG676I that I mentioned.
Do you need the extra power of the Kintex-Ultrascale FPGAs? Yes, if you need external RAM with DDR4 (see comments of coryb in <this> post).
So, perhaps the key question is, “Can we write 12-bit data to BRAM configured to hold 1.2Mb at a rate of 250MHz?”. I think the answer is yes - with suitable pipelining of the address inputs and data outputs of the BRAM. See <this> post for an example of BRAM pipelining. Note that this key question is something you can (and should) answer using Vivado Webpack software - before you buy any hardware.