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groverd
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Registered: ‎09-18-2009

Sensitivity list question

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I'm getting an Warning that my sensitivity list is missing certain signals.  I've actually done this on purpose but I wasn't sure if the tools allow this and essentially place them in the list anyway.  Basically I wanting to make sure that even if my process has 3 signals but only one of them is in my sensitivity list that when my other two signals change my process won't be entered.

 

Not sure if this will matter for this questions but I'm using Spartan II and Xilinx ISE 7.1a

 

Thanks in advance

Message Edited by groverd on 09-18-2009 10:40 AM
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bassman59
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Registered: ‎02-25-2008

groverd wrote:

I'm getting an Warning that my sensitivity list is missing certain signals.  I've actually done this on purpose but I wasn't sure if the tools allow this and essentially place them in the list anyway.  Basically I wanting to make sure that even if my process has 3 signals but only one of them is in my sensitivity list that when my other two signals change my process won't be entered.

 

Not sure if this will matter for this questions but I'm using Spartan II and Xilinx ISE 7.1a

 

Thanks in advance

Message Edited by groverd on 09-18-2009 10:40 AM

 

The problem with this is that your simulation may not match the synthesis results. 

Every signal on the right-hand-side of any assignment in a combinatorial process must be in the sensitivity list.

 

You say that you want the process to trigger on only one signal out of three. That's fine and dandy -- but the synthesis tool doesn't care. It will actually ignore the sensitivity list and build logic based on the assignments in the process. This means that your simulation won't trigger on the two signals but the synthesized logic WILL.

 

So you will have to be clever about how you write your combinatorial logic. Put all three signals are on the sensitivity list, and the one that rules them all might be used as a gate. 

 

----------------------------Yes, I do this for a living.

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bassman59
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Registered: ‎02-25-2008

groverd wrote:

I'm getting an Warning that my sensitivity list is missing certain signals.  I've actually done this on purpose but I wasn't sure if the tools allow this and essentially place them in the list anyway.  Basically I wanting to make sure that even if my process has 3 signals but only one of them is in my sensitivity list that when my other two signals change my process won't be entered.

 

Not sure if this will matter for this questions but I'm using Spartan II and Xilinx ISE 7.1a

 

Thanks in advance

Message Edited by groverd on 09-18-2009 10:40 AM

 

The problem with this is that your simulation may not match the synthesis results. 

Every signal on the right-hand-side of any assignment in a combinatorial process must be in the sensitivity list.

 

You say that you want the process to trigger on only one signal out of three. That's fine and dandy -- but the synthesis tool doesn't care. It will actually ignore the sensitivity list and build logic based on the assignments in the process. This means that your simulation won't trigger on the two signals but the synthesized logic WILL.

 

So you will have to be clever about how you write your combinatorial logic. Put all three signals are on the sensitivity list, and the one that rules them all might be used as a gate. 

 

----------------------------Yes, I do this for a living.

View solution in original post