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Posts: 1
Registered: ‎07-22-2017

Simple code for DDR3 SDRAM


I am very new at field of FPGA. Now I am working Genesys2. I have to control DDR3 memory. I find some examples in Digilent site for DDR3 using microblaze processor. But, in my case I don't have to use microblaze processor. I have to send some fixed value through the DDR3 memory like 8-bit data (X'FF') i.e. I will write that data into the Genesys2 DDR3 memory and readout the data from the memory. I already go through Xilinx network device video manual ug_586 . But still it is not clear to me how to start coding for the DDR3 memory. My questions are:

1) Is it possible to have example code without using microblaze processor for DDR3 memory?

Or any suggestion for starting code to control DDR3 memory.

Actually, I have do it in any way. So any helpful suggestion will be appreciated.

Thank you.

Posts: 1,845
Registered: ‎03-22-2016

Re: Simple code for DDR3 SDRAM


The simplest way is actually using the microblaze in standalone mode in my opinion.

It is supported by Vivado which is great

This getting started example already includes the DDR3 (on step 3) so just follow it. 


Then modify the Hello World example in SDK to peek/poke from memory. 

You can get the DDR3 memory location in the SDK (see picture under item 9.1 in the tutorial - "Memory Map for Processor microblaze_0"). In the example case DDR3 is between 0x80000000 - 0xBFFFFFFF so feel free to use it. Obviously watch out in the linker script where the program sections are located.

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Posts: 5,661
Kudos: 788
Solutions: 1,015
Registered: ‎09-20-2012

Re: Simple code for DDR3 SDRAM

Hi @carterturner


Check out MIG IP example design. If you are using User interface, refer to write path,command path, read path sections in UG586 for details on how to drive UI.

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Posts: 89
Registered: ‎05-21-2015

Re: Simple code for DDR3 SDRAM

The OpenArty project connects a ZipCPU (not a microblaze) to DDR3 SDRAM.  Even at that, the ZipCPU can be removed with by commenting a simple `ifdef at the top of the main file which will still give you access to the SDRAM from software running over a UART.  The SDRAM is then accessed over a wishbone bus.


A key component of the OpenArty approach to SDRAM memory access is the pipelined wishbone to AXI bridge.  I personally find the wishbone bus simpler to use than AXI.


All of the source code for that project is available on GitHub, although I did need the parameters from the Arty board configuration file (an xml file, hence readable) in order to get the DDR3 SDRAM configured properly.