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qizhong19920114
Adventurer
Adventurer
7,712 Views
Registered: ‎06-16-2014

State Machine goes wrong when no logic error.

Hi, the state machine I'm trying to debug doesn't seem to have any logic error but it goes to the wrong state everytime. what could be the causes of this? 

 

The attachment is file I am working with. The state should transit from IDLE state to TRANSPARENT_IDLE state given the input I have, but it instead goes to the XSYNC_XMIT_SYNC state. 

 

Any help would be really appreciated. 

 

*attachment removed by Forums admin

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

is this happening in hardware or simulation? If hardware, did you simulate the design ?
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qizhong19920114
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Registered: ‎06-16-2014

I haven't done simulation.  But the error happens everytime, does that suggest it's a logic error that can be observe in simulation? What can I do if it's hardaware problem? 

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Registered: ‎07-15-2008

just a thought, you posted an entire copyright design file in the public domain, if you don't have permission to do so, you could land in trouble!

Bobster
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Registered: ‎07-15-2008

the first thing Id do is check you are setup correctly...
Are you sure you are driving the inputs you think your driving?
Are you sure your reading the outputs you think your reading?

I guess your running tests with chipscop..

aka sanity check :-) done..

Time to simulate it...

Bobster
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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

>> I haven't done simulation. But the error happens everytime, does that suggest it's a logic error ...

Most probably yes. First simulate & verify that it works. Once you fix any issues, check how you are using the module: timing constraints properly set (any broken false paths, multicycles)? timing met? all asynchronous inputs synchronized properly for metastability ? all inputs synchronized to their respective clocks (ie clocks where they are sampled) ?
Then you can put in on the hardware again and add more signals to observe if you still can't make it work.
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qizhong19920114
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Registered: ‎06-16-2014

Could you please tell me how to check  broken false paths and multicycles from the synthesis report??

 

Thanks

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qizhong19920114
Adventurer
Adventurer
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Registered: ‎06-16-2014

I just did an experiment. In the case statement in IDLE state, I replace the section under 2'b01 with 

 

address_sent <= 1;
xmit_sync <= 0;
crc_ena <= 0;
shift_reg <= ones;
state <= TRANSPARENT_IDLE;

 

So it doesn't enter XSYNC_XMIT_SYNC from IDLE state, but I am still getting to the XSYNC_XMIT_SYNC state. What is the problem? 

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bassman59
Historian
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Registered: ‎02-25-2008


@qizhong19920114 wrote:

I haven't done simulation.  But the error happens everytime, does that suggest it's a logic error that can be observe in simulation? What can I do if it's hardaware problem? 


You should ALWAYS simulate and verify the design -- before you even think about synthesis and implementation! 

 

That is how you discover and fix logic errors.

 

If the logic is functionally correct, only then do you go to implementation, where the problems are of a different nature.

----------------------------Yes, I do this for a living.
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