09-19-2011 03:34 PM
I met a very strange issue when I was debugging with ChipScope.
I used ML605 board to control and communicate with a CMOS sensor via FMC HPC interface. My design was correctly simulated, but I was not successful to implement the design (Flag signals did not assert). Then I added ChipScope to debug, without any changing of code, my design has been successfully implemented. And all the signals are correctly displayed by ChipScope.
Furthermore, in an other design, I can not read out the correct data from a dual port ram only except adding a ChipScope debugger.
It really confuse me. Does ChipScope affect the timing of signals or it optimize signals' route and place?
I am grateful for any help.
09-19-2011 04:11 PM
09-19-2011 04:16 PM - edited 09-19-2011 04:57 PM
09-21-2011 07:17 AM
Thanks for your reply. I tried enabling the "ignore keep hierarchy", but the problem still existed, and both case have no timing error. It is really strange, and I have never succeed without adding ChipScope.
09-21-2011 07:20 AM
I am sure there are not timing constraint errors in both case. And I added the ChipScope without changing any properties. Any suggestions? I am using ISE 12.4 version
09-21-2011 07:33 AM
I'd still suspect timing. What frequencies are you targeting? What TIGs are in your ucf file? Are you sure that all your constraints are correct? Have you properly constrained all IOs for setup/hold times?
Where I've had problems such as yours - adding chipscope changing the behaviour - it's usually a problem with my constraints. I've mistakenly applied constraints, or incorrectly created false paths.
My experience anyway.
Other things to consider with respect to missed timing:
09-21-2011 08:29 AM
As mark said. List the clicks you are using, and what constraints you have associated with them. Are all of your clocks on global or regional clock buffers?
09-22-2011 03:55 AM
Many thanks for your reply, it is really helpful.
I am very new to FPGA, and I can not understand timing constraints well.
For my application (ucf file), I just map the in/out port to the correct pin and only define the timing constraint of the Global clock signals. is this the main problem of the issue?
I attached my ucf file, and if you can have a quick look , I will be very grateful.
09-22-2011 01:39 PM
You're contraining clocks in the UCF, that's good. But not IO - that's bad. Let's skip IO for now, (not a safe assumption at all but we've got to start somewhere.). When you run trce, what do you get at the output? It should say something like:
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
What results do you see? Any non-zero results? I have a suspicion that you're not going to see all zeros here. I could be wrong...