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Newbie
Newbie
2,067 Views
Registered: ‎05-02-2010

Strange map report

Hi all, I recently tried to make simple n to 1 multiplexer with selection input. It just forward to output one part of input stdlogicvector, based on selection value. When I put selection 2 and width 10 as in code below, I get zero gate count in map report. When I put 2 and 32 I get value different than zero. Anybody has some idea? Cheers entity mltplx is generic( selection : integer:=2; width : integer:=10 ); port( input : in std_logic_vector((2**selection)*width-1 downto 0); sel : in std_logic_vector(selection-1 downto 0); output : out std_logic_vector(width-1 downto 0) ); end mltplx; architecture arch of mltplx is begin mux: process(input, sel) variable i : integer; begin i := conv_integer(unsigned(sel)); output <= input((i+1)*width-1 downto i*width); end process; end arch;
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Xilinx Employee
Xilinx Employee
2,012 Views
Registered: ‎09-07-2009

Hi lutteur,

  you shouldn't write the code like this. 

  All the code you wrote will be turned to circuit.

  So, unlike software codes, you must imagine the circuit when you write HDL.

  I advice you use "CASE".

 

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